Derek Basehore 5a5dc61713 rockchip: rk3399: Fix CAS latency setting ... The F1 CAS latency setting was not bit shifted, which resulted in setting the DRAM additive latency value instead. Signed-off-by: Derek Basehore <dbasehore@chromium.org>		2017-02-24 20:07:45 +08:00
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dram	rockchip: rk3399: Fix CAS latency setting	2017-02-24 20:07:45 +08:00
gpio	rockchip/rk3399: improve gpio driver and support get pull mode function	2016-09-10 04:06:39 +08:00
m0	rockchip: rk3399: Move DQS drive strength setting to M0	2017-02-24 20:07:45 +08:00
pmu	rockchip: rk3399: Clean up and seprate secure parts from SoC codes	2017-02-24 20:07:45 +08:00
pwm	rockchip: update to handle PWMs for rk3399	2016-08-11 13:09:28 +08:00
secure	rockchip: rk3399: Clean up and seprate secure parts from SoC codes	2017-02-24 20:07:45 +08:00
soc	rockchip: rk3399: Clean up and seprate secure parts from SoC codes	2017-02-24 20:07:45 +08:00