Derek Basehore 5a5dc61713 rockchip: rk3399: Fix CAS latency setting ... The F1 CAS latency setting was not bit shifted, which resulted in setting the DRAM additive latency value instead. Signed-off-by: Derek Basehore <dbasehore@chromium.org>		2017-02-24 20:07:45 +08:00
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dfs.c	rockchip: rk3399: Fix CAS latency setting	2017-02-24 20:07:45 +08:00
dfs.h	rockchip: rk3399: add support for ddrfreq suspend/resume	2017-02-24 20:07:44 +08:00
dram.c	rockchip: rk3399: Clean up and seprate secure parts from SoC codes	2017-02-24 20:07:45 +08:00
dram.h	rockchip: rk3399: Save and restore RX_CAL_DQS values	2017-02-24 20:07:45 +08:00
dram_spec_timing.c	rockchip: rk3399: dram: remove dram_init and dts_timing_receive function	2017-02-24 15:43:47 +08:00
dram_spec_timing.h	rockchip: Break out common dram code for rk3399	2016-10-27 01:50:57 +08:00
suspend.c	rockchip: rk3399: Save and restore RX_CAL_DQS values	2017-02-24 20:07:45 +08:00
suspend.h	rockchip: add support save/restore configuration for DDR during enter S3	2016-10-27 07:14:26 +08:00