Boon Khai Ng 447e699f70 feat(intel): add macro to switch between different UART PORT ... HSD #1509626040: This patch is to add the flexibility for BL2 and BL31 to choose different UART output port at platform_def.h using parameter PLAT_INTEL_UART_BASE This patch also fixing the plat_helpers.S where the UART BASE is hardcoded to PLAT_UART0_BASE. It is then switched to CRASH_CONSOLE_BASE. Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Change-Id: Iccfa7ec64e4955b531905778be4da803045d3c8f		2022-04-05 14:25:30 +08:00
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aarch64	feat(intel): add macro to switch between different UART PORT	2022-04-05 14:25:30 +08:00
drivers	build(intel): enable access to on-chip ram in BL31 for N5X	2022-03-09 09:14:26 +08:00
include	feat(intel): add macro to switch between different UART PORT	2022-04-05 14:25:30 +08:00
sip	feat(intel): add SMC support for ROM Patch SHA384 mailbox	2022-04-05 14:23:26 +08:00
soc	build(intel): add N5X as a new Intel platform	2022-03-09 09:14:03 +08:00
bl2_plat_mem_params_desc.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00
socfpga_delay_timer.c	plat: intel: Additional instruction required to enable global timer	2020-06-08 22:03:54 +00:00
socfpga_image_load.c	intel: Implement platform specific system reset 2	2019-12-30 10:17:04 +08:00
socfpga_psci.c	fix(intel): fix ECC Double Bit Error handling	2022-03-09 09:14:16 +08:00
socfpga_sip_svc.c	feat(intel): add SMC support for ROM Patch SHA384 mailbox	2022-04-05 14:23:26 +08:00
socfpga_storage.c	intel: Refactor common platform code [2/5]	2019-11-28 12:47:58 +08:00
socfpga_topology.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00