On STM32MP13, OP-TEE will be loaded at the beginning of the secure
memory, and will be responsible for its shared memory.
The memory allocated to OP-TEE is then 32MB, and the shared memory
does no more appear in the STM32MP13 fw-config DT file.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4e9238ddb4d82079b9ddf8fc8f6916b5b989d263
Remove the nvmem_layout node with compatible "st,stm32-nvmem-layout"
no more used in TF-A code to simplify the device tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I3748b20b7d3c60ee64ead15541fac1fd12656600
Add dedicated device tree files for STM32MP13.
Add new DDR compatible for STM32MP13x.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ib1bb9ad8cb2ab9f5f81549635d6604093aeb99d3
To be able to load images with FIP and FCONF on STM32MP13,
the st-io_policies has to be filled.
It is a copy of the node in stm32mp15_bl2.dtsi .
Change-Id: Ia15f50d1179e9b8aefe621dc5e0070ea845d6aac
Signed-off-by: Yann Gautier <yann.gautier@st.com>
STM32MP13 is a single Cortex-A7 CPU, without co-processor.
As for STM32MP15x SoC family, STM32MP15x SoCs come with different
features, depending on SoC version. Each peripheral node is created.
Some are left empty for the moment , and will be filled later on.
Change-Id: I0166bb70dfa7f717e89e89883b059a5b873c4ef7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
* changes:
fix(sptool): add leading zeroes in UUID conversion
feat(tc): enable SMMU for DPU
feat(tc): add reserved memory region for Gralloc
feat(tc): enable GPU
fix(tc): remove the bootargs node
The SMMU needs to be enabled to support 8GB RAM
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ie81f2fc59886c52e9d6ed799ea73f49eb7a7c307
Gralloc for Android S uses dmabuf, we need to add reserved memory area
for these allocations
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: If869ac930fadc374ec435cae3847ba374584275b
Add DTS node for GPU to support hardware rendering in Android
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: I2cf2badf5b15e59a910f6cf7d3d30fdfaf4fe9ce
We need to keep the kernel command line in Yocto, otherwise we
can't support AVB.
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ic291eb13620b307f10354c2c2797c6fc9b053e83
Set non-secure property on platform secure OTP nodes that non-secure
world is allowed to access through secure world services.
These are the SoC MAC address and the ST boards board_id OTPs.
Most of these were already done but it was missing for ED1 board.
Change-Id: Idfa6322d9d5c35285706d0b2d32ae09af38684a7
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
A new nvmem_layout node includes nvmem platform-dependent layout
information, such as OTP NVMEM cell lists (phandle, name).
This list allows easy access to OTP offsets defined in BSEC node,
where more OTP definitions with offsets in bytes and length have
been added (replace hard-coded values).
Each board may redefine this list, especially for board_id info.
Change-Id: I910ae671b3bf3320ee6500fecc9ec335ae67bbda
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
If a board declares an mmc1 alias in its DT and is compiled without flags
STM32MP_EMMC or STM32MP_SDMMC, the DT will fail to build.
Add /delete-property/ mmc1; to correct this.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I1938ff99dc3d883f9174ee886f9ffa195ec60373
Total Compute has ETE and TRBE tracing components and they have
to be enabled to capture the execution trace of the processor.
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I3c86c11be2c655a61ecefa3eb2e4e3951577a113
The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when built-in calibration is executed.
The calibration parameters were provided in the device tree by the
optional node "st,phy-cal", activated in ddr helper file by the
compilation flag DDR_PHY_CAL_SKIP and filled with values generated
by CubeMX.
This patch
- updates the binding file to remove "st,phy-cal" support
- updates the device trees and remove the associated defines
- simplifies the STM32MP1 DDR driver and remove the support of
the optional "st,phy-cal"
After this patch the built-in calibration is always executed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I3fc445520c259f7f05730aefc25e64b328bf7159
Update regulator description to match with pmic driver updates.
vref_ddr does not support over-current protection.
vtt_ddr is set to sink source mode.
Change-Id: I725f35b091ca8c230994c2b5f81693ebc97bf4aa
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Add 'firmware' node in morello-soc.dts to expose SCMI
support to the kernel. The SCMI protocols supported at
the moment are SCMI Base, Clock and Perf (DVFS).
The current mailbox memory region in MHU SRAM has an issue
with any access not aligned to a 4-byte boundary. So, the SCMI
mailbox memory region has been relocated to AP non-trusted
RAM to get around the problem.
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Change-Id: Ibcbce8823b751a0fc3be7e9bc3588c1dc47ae024
Morello Specification specifies the system
reference clock frequency as 50MHz so the frequency
has been changed from 100MHz to 50MHz.
Change-Id: I25577b04aa54ed82b7e9df69ac8e40ac54a9b111
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* changes:
feat(arm_fpga): write UART baud base clock frequency into DTB
feat(arm_fpga): query PL011 to learn system frequency
refactor(arm_fpga): move command line code into separate function
fix(fdt): avoid output on missing DT property
feat(arm_fpga): add ITS autodetection
feat(arm_fpga): determine GICR base by probing
feat(gicv3): introduce GIC component identification
feat(libfdt): also allow changing base address
fix(arm_fpga): avoid re-linking from executable ELF file
Add 2021 year in the file header Copyright line.
Change-Id: I09f7bef1f746c429ff308286169354e58648a1cd
Signed-off-by: Yann Gautier <yann.gautier@st.com>
About a year ago there was a change in the underlying Arm platform design
framework, which lead to a reorganisation of the interrupt map (to make
room for multi-chip designs).
This lead to the PL011 debug UART interrupt to move from SPI 115 to SPI
415. Unfortunately there is not a good or easy way to auto-detect this
change: Flooding the TX FIFO and checking GICD_ISPENDR registers might
be possible, but sounds a bit over the top for BL31.
So we would need to break one group of images: newer ones, as we do right
now, or older ones.
By now every interesting FPGA image seems to use the newer IRQ, so in
the interest of having a smooth experience for most users, lets switch
to this IRQ.
When people are interested in older images, they can either change the
number back in the .dts file, or provide a patched DTB on the FPGA
command line.
Change-Id: I3c7e7b711f5142813bd94eecde3095a4fc555bb3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The Arm FPGAs run in mostly one clock domain, which is used for the CPU
cores, the generic timer, and also the UART baudrate base clock. This
single clock can have different rates, to compensate for different IP
complexity. So far most images used 10 MHz, but different rates start to
appear.
To avoid patching both the arch timer frequency and UART baud base fixed
clock in the DTB manually, we would like to set the clock rate
automatically. Fortunately the SCP firmware has the actual clock rate
hard coded, and already programs the PL011 UART baud divider register
with the correct value to achieve a 38400 bps baudrate.
So read the two PL011 baudrate divider values and re-calculate the
original base clock from there, to use as the arch timer frequency. If
the arch timer DT node contains a clock-frequency property, we use that
instead, to support overriding and disabling this autodetection.
Change-Id: I9857fbb418deb4644aeb2816f1102796f9bfd3bb
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Some FPGAs come with a GIC that has an ITS block configured. Since the
ITS sits between the distributor and redistributors, we can autodetect
that, and already adjust the GICR base address.
To also make this ITS usable, add an ITS node to our base DTB, and
remove that should we not find an ITS during the scan for the
redistributor. This allows to use the same TF-A binary for FPGA images
with or without an ITS.
Change-Id: I4c0417dec7bccdbad8cbca26fa2634950fc50a66
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* changes:
fix(fdts stm32mp1): update PLL nodes for ED1/EV1 boards
fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards
feat(fdts stm32mp1): delete nodes for non-used boot devices
fix(fdts stm32mp1): use 'kHz' as kilohertz abbreviation
refactor(fdts stm32mp1): move STM32MP DDR node
feat(fdts stm32mp1): align DT with latest kernel
Align STM32MP157C-ED1/EV1 boards PLL nodes with what is done
for DK boards.
Change-Id: I91be408ea1d9b0474caf4965175df33792b7e11e
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Set Ethernet source clock on PLL4P. This is required to enable PTP.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ia64fbb681d3f04f2b90f373c5eb044f5daa2836c
Cleanup the BL2 device tree file by removing the nodes for the devices
that are not used to boot, depending on compilation flags.
In SDMMC boot, the gain for the dtb file is about 2.3kB.
Change-Id: I3ba13e06dd22b52cff96f51db2dac94b532c81ae
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The kilohertz unit abbreviation should read 'kHz' in DDR
settings files of stm32mp15.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifa363094f58dd943ef78c653c3e470a216739b41
Move the generic part of DDR node in SOC dtsi file.
DDR dtsi files only include the part configured by CubeMX tool.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I8c211e9782604da32aeaab98d0ef75fb1cd9c58d
This change enables MPMM and adds, to the TC firmware configuration
device tree, the AMU counters representing the "gears" for the
Maximum Power Mitigation Mechanism feature of the Cortex-X2,
Cortex-A710 and Cortex-A510:
- Gear 0: throttle medium and high bandwidth vector and viruses.
- Gear 1: throttle high bandwidth vector and viruses.
- Gear 2: throttle power viruses only.
This ensures these counters are enabled and context-switched as
expected.
Change-Id: I6df6e0fe3a5362861aa967a78ab7c34fc4bb8fc3
Signed-off-by: Chris Kay <chris.kay@arm.com>
* changes:
refactor(gpt): productize and refactor GPT library
feat(rme): disable Watchdog for Arm platforms if FEAT_RME enabled
docs(rme): add build and run instructions for FEAT_RME
fix(plat/fvp): bump BL2 stack size
fix(plat/fvp): allow changing the kernel DTB load address
refactor(plat/arm): rename ARM_DTB_DRAM_NS region macros
refactor(plat/fvp): update FVP platform DTS for FEAT_RME
feat(plat/arm): add GPT initialization code for Arm platforms
feat(plat/fvp): add memory map for FVP platform for FEAT_RME
refactor(plat/arm): modify memory region attributes to account for FEAT_RME
feat(plat/fvp): add RMM image support for FVP platform
feat(rme): add GPT Library
feat(rme): add ENABLE_RME build option and support for RMM image
refactor(makefile): remove BL prefixes in build macros
feat(rme): add context management changes for FEAT_RME
feat(rme): add Test Realm Payload (TRP)
feat(rme): add RMM dispatcher (RMMD)
feat(rme): run BL2 in root world when FEAT_RME is enabled
feat(rme): add xlat table library changes for FEAT_RME
feat(rme): add Realm security state definition
feat(rme): add register definitions and helper functions for FEAT_RME
This patch make minor modifications to FVP DTS including modifying
the Non-secure memory range when RME is enabled.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I6b3650a2abfff10462a8a2d42755e6d764f7b035
Add support for Arm Ethos-N NPU multi-device.
The device tree parsing currently only supports one NPU device with
multiple cores. To be able to support multi-device NPU configurations
this patch adds support for having multiple NPU devices in the device
tree.
To be able to support multiple NPU devices in the SMC API, it has been
changed in an incompatible way so the API version has been bumped.
Signed-off-by: Laurent Carlier <laurent.carlier@arm.com>
Change-Id: Ide279ce949bd06e8939268b9601c267e45f3edc3
Add the UUID into the io policies node that are retrieved
by BL2 using stm32mp_fconf_io.c populate function.
Change-Id: I595d5a41a1e0a27fcc02ea2ab5495d9dbf0e6773
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Create all boards fw-config DT files. They all include a generic
stm32mp15-fw-config.dtsi.
Change-Id: Ib9ac8a59e93e01365001b0d11fee41f7c507c08e
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
BL2 still uses the STM32 header binary format to be loaded from ROM code.
BL32 and BL33 and their respective device tree files are now put together
in a FIP file.
One DTB is created for each BL. To reduce their sizes, 2 new dtsi file are
in charge of removing useless nodes for a given BL. This is done because
BL2 and BL32 share the same device tree files base.
The previous way of booting is still available, the compilation flag
STM32MP_USE_STM32IMAGE has to be set to 1 in the make command. Some files
are duplicated and their names modified with _stm32_ to avoid too much
switches in the code.
Change-Id: I1ffada0af58486d4cf6044511b51e56b52269817
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
This renames tc0 platform folder and files to tc, and introduces
TARGET_PLATFORM variable to account for the differences between
TC0 and TC1.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I5b4a83f3453afd12542267091b3edab4c139c5cd
* changes:
feat(tc0): add cpu capacity to provide scheduling information
fix(tc0): remove "arm,psci" from psci node
feat(tc0): update mhuv2 dts node to align with upstream driver
"arm,psci" expects the FIDs for cpu-on, cpu-off and cpu-suspend, which
arent present in the device tree, so remove it from psci compatible.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: Icd1ce8ec7fd3f270925e4b3d5d0187088ffe4ba5
The MHUv2 driver has been merged upstream, and it has a different
dts format compared to what was previously used. This patch aligns
with the upstream driver.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: Ic963c21c1475d301c3a75686718e6e17841831c3
Yann Gautier
Rupinderjit Singh
Patrick Delaunay
Nicolas Le Bayon
Manish Pandey
Anders Dellien
Davidson K
Pascal Paillet
Anurag Koul
Manoj Kumar
Madhukar Pappireddy
André Przywara
Yann Gautier
Nicolas Le Bayon
Chris Kay
Usama Arif
Soby Mathew
Zelalem Aweke
Laurent Carlier
Lionel Debieve
Olivier Deprez