This patch submits an RFC to refactor the context management
mechanism in TF-A.
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: Ia1ad5a85cb86c129e2feaf36bed123f0067c3965
Cortex-A510 erratum 2041909 is a Cat B erratum that applies to revision
r0p2 and is fixed in r0p3. It is also present in r0p0 and r0p1 but there
is no workaround in these revisions.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7b1498faa0c79488dee0d11d07f6e9f58144e298
Cortex-A510 erratum 2042739 is a Cat B erratum that applies to revisions
r0p0, r0p1 and r0p2 and is fixed in r0p3.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I1d2ebee3914396e1e298eb45bdab35ce9e194ad9
Cortex-A510 erratum 2288014 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I875519ff55be90244cc3d3a7e9f7abad0fc3c2b8
Cortex-A510 erratum 1922240 is a Cat B erratum that applies to revision
r0p0 and is fixed in r0p1.
Since no errata framework code existed for A510 prior to this patch, it
has been added as well. Also some general cleanup changes in the CPU lib
makefile.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I8c427ef255cb4b38ed3e5c2c7444fcef957277e4
* changes:
docs(layerscape): add ls1046a soc and board support
feat(ls1046aqds): add board ls1046aqds support
feat(ls1046afrwy): add ls1046afrwy board support
feat(ls1046ardb): add ls1046ardb board support
feat(ls1046a): add new SoC platform ls1046a
fix(nxp-tools): fix tool location path for byte_swape
fix(nxp-qspi): fix include path for QSPI driver
build(changelog): add new scopes for NXP layerscape platforms
On Debian systems it is possible to use system-wide Crypto++ library.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ib01d9376776b8afcb1ca46c16076e28c3d2e581d
Update document for nxp-layerscape to add ls1046a SoC and ls1046ardb,
ls1046afrwy board support.
Also update maintainer of ls1046a platforms.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I522f978bc93aa8d1f1d60fa8efef392b7d854df7
Armada 3720 BootROM searches for GPT partition with partition type GUID
6828311A-BA55-42A4-BCDE-A89BB5EDECAE and completely ignores GPT
partition name. It does not check for "MARVELL BOOT PARTITION".
This fact is incorrectly documented even in official Marvell Armada 3700
Functional Specification.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I35279f39de2d12148fc16f2730a9a074dc0b58eb
diphda platform is now being renamed to corstone1000.
These changes are to replace all the instances and traces
of diphda corstone1000.
Change-Id: I330f3a112d232b99b4721b6bf0236253b068dbba
Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Added a couple of sub-sections (Coverity Scan and Test Configuration)
under "Add build configuration" to update the patch owners on the
sections they need to be aware of while introducing new source files.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I84adb182f9633863aac864df43578249c2269c1e
Cortex-A710 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR5_EL1[44] to 1 which will cause
the CPP instruction to invalidate the hardware prefetcher state
trained from any EL.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I43a86a365418fb663cc1b6ab1d365b4beddae0bc
Cortex-A710 erratum 2267065 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR_EL1[22] to 1'b1. Setting
CPUACTLR_EL1[22] will cause the CFP instruction to invalidate
all branch predictor resources regardless of context.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia9085aaf9b2b6a2b25d03ab36bd3774839fac9aa
Cortex-X2 erratum 2216384 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR5_EL1[17] to 1'b1 followed by
applying an instruction patching sequence.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I3c216161678887c06a28c59644e784e0c7d37bab
Cortex-X2 erratum 2081180 is a Cat B erratum present in r0p0, r1p0
and r2p0 of the Cortex-X2 processor core.
Cortex-X2 SDEN: https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I64bed2fd5b7e12932d6de2ae668786e689885188
Cortex-X2 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0. The workaround is to set CPUECLTR_EL1[8]
to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I3b740aedc95c2394f6b8d1186014d2b2f640ae05
The Qualcomm Snapdragon 410 is Qualcomm's first 64-bit SoC, released
in 2014 with four ARM Cortex-A53 cores. There are differents variants
(MSM8916, APQ8016(E), ...) that are all very similar. A popular device
based on APQ8016E is the DragonBoard 410c single-board computer,
but the SoC is also used in various mid-range smartphones/tablets.
This commit adds documentation for a minimal, community-maintained port
of TF-A/BL31 for MSM8916. The actual platform port is added in the
following four separate small commits to simplify the review process.
The code is primarily based on the information from the public
Snapdragon 410E Technical Reference Manual [1], combined with a lot of
trial and error to actually make it work.
Note that this port is a pure community effort without any
commercial interests and is not related to Qualcomm in any way.
The main motivation for this port is to have a minimal, updatable
firmware since this old chip does not receive many updates anymore from
Qualcomm. It works quite well for many use cases so I am willing to
maintain it as a "code owner". I have also added Nikita Travkin as
second code owner to help with reviews.
The main limitation so far is the lack of memory protection for TF-A.
This is similar to the ports for the Raspberry Pi but in this case not
a lack of hardware support but rather a lack of documentation. However,
this does not limit the usefulness of the port when used as a minimal
PSCI implementation.
[1]: https://developer.qualcomm.com/download/sd410/snapdragon-410e-technical-reference-manual.pdf
Change-Id: I676adf86061638cfc2f3ae8615470d145e84f172
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Add a platform hook for returning the boot index, i.e. the bank from
which the platform has booted the updatable firmware images. This
value will be passed to the Update Agent.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Change-Id: Ic7bef21071c48cfc7b69c50e89df9ff758d95b00
The metadata structure copy is passed to the platform routine to set
the image source to boot the platform from. This is done by reading
the metadata structure. Pass the metadata as a read-only copy to the
routine -- the routine only needs to consume the metadata values and
should not be able to update the metadata fields.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Change-Id: I399cad99ab89c71483e5a32a1de0e22df304f8b0
* changes:
build(npm): mandate Node.js engine version
docs(changelog): fix broken version bumping
docs(changelog): fix version tag links
refactor(hooks): replace cz-conventional-changelog with cz-commitlint
style(commitlint): reorder header/body max line length fields
chore(npm): update package versions/license
The Standard Version tool will not recognize a release header as a
release header without the minor version, and will overwrite them when
generating the next release changelog.
Additionally, it will not generate a link to the tag diff unless a tag
of the form `vX.Y.Z` exists. We ought to generate tags with this version
format in the future to ensure the diff links are generated.
Change-Id: I7864ab7a5822f83ddb7a7917208d2d029ae34729
Signed-off-by: Chris Kay <chris.kay@arm.com>
This change replaces cz-conventional-changelog with cz-commitlint, which
automatically configures Commitizen using our commitlint configuration
file. Currently, we use some manual Javascript magic to load our
Commitizen configuration into commitlint (the opposite of what's
introduced by this change), which can be removed.
With this change, we also move our commitlint configuration into a
new `changelog.yaml` file. This file holds the same data as `.cz.json`
previously did.
Change-Id: I14ff2308f1a0b2b293c2128b28ca2df578ce9c1c
Signed-off-by: Chris Kay <chris.kay@arm.com>
Added myself to be NXP common code and ls1028a, ls1043a platforms
maintainer.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iadffc5600e9bb2e94b1d545b8dd1a819358cabcb
Update document for nxp-layerscape to add ls1043a SoC and ls1043ardb
board support.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I8442daf08a0f7c1ba982a3ed1d0ad24c4c420185
Remove old implementation for Layerscape ls1043a platform, and
will added it back with unified software architecture of all
Layerscape platforms.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: If038c19ab04d70050ec8e6ab2097b1c4f8324e87
Measured-Boot and Trusted-Boot are orthogonal to each other and hence
removed dependency of Trusted-Boot on Measured-Boot by making below
changes -
1. BL1 and BL2 main functions are used for initializing Crypto module
instead of the authentication module
2. Updated Crypto module registration macro for MEASURED_BOOT with only
necessary callbacks for calculating image hashes
3. The 'load_auth_image' function is now used for the image measurement
during Trusted or Non-Trusted Boot flow
Change-Id: I3570e80bae8ce8f5b58d84bd955aa43e925d9fff
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Our list of possible Allwinner build targets was missing the newly
introduced R329 support. Fix that by adding a table with maps the SoC
names to the build target names.
Also add some explanation about the recently introduced PSCI power
management providers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Icf5e304562c3082552bf08d7b26904caf9074936
Document the newly introduced SUNXI_SETUP_REGULATORS build option, that
allows to disable PMIC regulator setup at build time.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie5fb0b7220426b67cfffc95df4cabb31a6ec174a
Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.
There are 2 ways this workaround can be accomplished, the first of
which involves executing a few additional instructions around MSR
writes to CPUECTLR when disabling the prefetcher. (see SDEN for
details)
However, this patch implements the 2nd possible workaround which sets
the prefetcher into its most conservative mode, since this workaround
is generic.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Idb20d9928c986616cd5bedf40bb29d46d384cfd3
Cortex X2 erratum 2002765 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I11576a03bfd8a6b1bd9ffef4430a097d763ca3cf
Cortex X2 erratum 2083908 is a Cat B erratum present in the Cortex
X2 core. It applies to revision r2p0 and is still open.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Id9dca2b042bf48e75fb3013ab37d1c5925824728
Threat model for the current, BL1-only R-class support.
Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I8479d5cb30f3cf3919281cc8dc1f21cada9511e0
Document `boot-order` field from FF-A partitions manifest, in accordance
to Hafnium's (SPM) implementation.
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I9fd070100ee52e0d465d2cce830cc91d78bddfc0
This patch adds macros explicit to the features - FEAT_FGT,FEAT_AMUv1
and FEAT_ECV respectively. It assists in controlled access to the set
of registers (HDFGRTR_EL2, HAFGRTR_EL2 and CNTPOFF_EL2) under the
influence of these features during context save and restore routines.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I5082ea6687a686d8c5af3fe8bf769957cf3078b0
Bipin Ravi
Soby Mathew
Madhukar Pappireddy
johpow01
Pali Rohár
Jiafei Pan
Vishnu Banavath
Ying-Chun Liu (PaulLiu)
Jayanth Dodderi Chidanand
Stephan Gerhold
Sughosh Ganu
Joanna Farley
Sandrine Bailleux
Chris Kay
Manish V Badarkhe
André Przywara
Mark Dykes
Gary Morrison
J-Alves
Manish Pandey