Commit Graph

651 Commits

Author SHA1 Message Date
Heiko Stuebner c6c10b02b8 Fixup register handling in aarch32 reset_handler
The BL handover interface stores the bootloader arguments in
registers r9-r12, so when the reset_handler stores the lr pointer
in r10 it clobers one of the arguments.

Adapt to use r8 and adapt the comment about registers allowed
to clober.

I've checked aarch32 reset_handlers and none seem to use higher
registers as far as I can tell.

Fixes: a6f340fe58 ("Introduce the new BL handover interface")
Cc: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-03-08 15:35:30 +00:00
Antonio Niño Díaz af3816789d
Merge pull request #1842 from DavidPu/reduce_cyclomatic_complexity_metric
Reduce cyclomatic complexity metric
2019-03-01 12:43:17 +00:00
Antonio Niño Díaz a4acc7f165
Merge pull request #1751 from vwadekar/tegra-scatter-file-support
Tegra scatter file support
2019-03-01 11:23:58 +00:00
Antonio Niño Díaz 37118a1b5f
Merge pull request #1849 from loumay-arm/lm/a73_errata
Cortex-A73: Implement workaround for errata 852427
2019-03-01 11:23:48 +00:00
Antonio Niño Díaz 4476838ae8
Merge pull request #1845 from ambroise-arm/av/errata
Apply workarounds for errata of Cortex-A53, A55 and A57
2019-03-01 09:17:27 +00:00
Antonio Niño Díaz 82842004f6
Merge pull request #1846 from loumay-arm/lm/mpam
MPAM: enable MPAM EL2 traps
2019-03-01 09:17:16 +00:00
Antonio Niño Díaz dbd0bcfe00
Merge pull request #1848 from antonio-nino-diaz-arm/an/docs
Minor changes to documentation and comments
2019-03-01 09:16:58 +00:00
David Pu e664b5b6ae xlat_tables_v2: find VA/idx with helper functions.
This patch introduces 2 helper functions 'xlat_tables_find_start_va' and
'xlat_tables_va_to_index' to find the first VA and table index affected by the
specified mmap region. it reduces code duplication and cyclomatic code
complexity in xlat_tables_map/unmap_region functions.

Cyclomatic complexity calculated using 'Coverity'

fixes arm-software/tf-issues#673

Signed-off-by: David Pu <dpu@nvidia.com>
2019-02-28 10:14:20 -08:00
David Pu 3ff6e401f9 xlat_tables_v2: get unmap action type with helper function.
This patch introduces helper function 'xlat_tables_unmap_region_action'
to get the required action type from given arguments when unmapping the
specified region.
it reduces cyclomatic code complexity in xlat_tables_unmap_region function.

Cyclomatic complexity calculated using 'Coverity'

fixes arm-software/tf-issues#673

Signed-off-by: David Pu <dpu@nvidia.com>
2019-02-28 09:58:16 -08:00
Antonio Nino Diaz 73308618fe Minor changes to documentation and comments
Fix some typos and clarify some sentences.

Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-28 13:35:21 +00:00
Louis Mayencourt 25278eaba7 Cortex-A73: Implement workaround for errata 852427
In AArch32, execution of 2 instructions with opposite condition code
might lead to either a data corruption or a CPU deadlock. Set the bit
12 of the Diagnostic Register to prevent this.

Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-28 12:01:13 +00:00
Louis Mayencourt 537fa85917 MPAM: enable MPAM EL2 traps
Complete the MPAM enablement in TF-A for lower ELs by enabling the EL2
traps in MPAMHCR_EL2 and MPAM2_EL2.This prevents an
MPAM-unaware-hypervisor to be restricted by an MPAM-aware-guest.

Change-Id: I47bf3f833fa22baa590f83d49cc0e3f2974e698d
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-28 10:28:25 +00:00
Antonio Niño Díaz 64503b2f81
Merge pull request #1839 from loumay-arm/lm/a7x_errata
Cortex-A73/75/76 errata workaround
2019-02-28 10:19:24 +00:00
Ambroise Vincent bd393704d2 Cortex-A53: Workarounds for 819472, 824069 and 827319
The workarounds for these errata are so closely related that it is
better to only have one patch to make it easier to understand.

Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28 09:56:58 +00:00
Ambroise Vincent 5bd2c24f17 Cortex-A57: Implement workaround for erratum 817169
Change-Id: I25f29a275ecccd7d0c9d33906e6c85967caa767a
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28 09:56:58 +00:00
Ambroise Vincent 0f6fbbd2e5 Cortex-A57: Implement workaround for erratum 814670
Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28 09:56:58 +00:00
Ambroise Vincent 47949f3f83 Cortex-A55: Implement workaround for erratum 903758
Change-Id: I07e69061ba7a918cdfaaa83fa3a42dee910887d7
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28 09:56:58 +00:00
Ambroise Vincent 6e78973ea2 Cortex-A55: Implement workaround for erratum 846532
Change-Id: Iacb6331c1f6b27340e71279f92f147ebbc71862f
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28 09:56:58 +00:00
Ambroise Vincent 6ab87d2981 Cortex-A55: Implement workaround for erratum 798797
Change-Id: Ic42b37b8500d5e592af2b9fe130f35a0e2db4d14
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28 09:56:58 +00:00
Ambroise Vincent a6cc661016 Cortex-A55: Implement workaround for erratum 778703
Change-Id: I094e5cb2c44618e7a4116af5fbb6b18078a79951
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28 09:56:58 +00:00
Ambroise Vincent 1afeee9275 Cortex-A55: Implement workaround for erratum 768277
Change-Id: Iebd45ef5e39ee7080235fb85414ce5b2e776f90c
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28 09:56:58 +00:00
Varun Wadekar c2ad38ce4f Tegra: Support for scatterfile for the BL31 image
This patch provides support for using the scatterfile format as
the linker script with the 'armlink' linker for Tegra platforms.

In order to enable the scatterfile usage the following changes
have been made:

* provide mapping for ld.S symbols in bl_common.h
* include bl_common.h from all the affected files
* update the makefile rules to use the scatterfile and armlink
  to compile BL31
* update pubsub.h to add sections to the scatterfile

NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY.

Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-02-27 08:33:35 -08:00
Antonio Nino Diaz b86048c40c Add support for pointer authentication
The previous commit added the infrastructure to load and save
ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but
didn't actually enable pointer authentication in the firmware.

This patch adds the functionality needed for platforms to provide
authentication keys for the firmware, and a new option (ENABLE_PAUTH) to
enable pointer authentication in the firmware itself. This option is
disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be
enabled.

Change-Id: I35127ec271e1198d43209044de39fa712ef202a5
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27 11:58:09 +00:00
Antonio Nino Diaz 5283962eba Add ARMv8.3-PAuth registers to CPU context
ARMv8.3-PAuth adds functionality that supports address authentication of
the contents of a register before that register is used as the target of
an indirect branch, or as a load.

This feature is supported only in AArch64 state.

This feature is mandatory in ARMv8.3 implementations.

This feature adds several registers to EL1. A new option called
CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save
them during Non-secure <-> Secure world switches. This option must be
enabled if the hardware has the registers or the values will be leaked
during world switches.

To prevent leaks, this patch also disables pointer authentication in the
Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will
be trapped in EL3.

Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27 11:08:59 +00:00
Antonio Nino Diaz 4d1ccf0ecc Cleanup context handling library
Minor style cleanup.

Change-Id: Ief19dece41a989e2e8157859a265701549f6c585
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27 11:08:59 +00:00
Louis Mayencourt 5c6aa01aff Add workaround for errata 1073348 for Cortex-A76
Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.

Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-26 16:21:06 +00:00
Louis Mayencourt 5cc8c7ba1b Add workaround for errata 1220197 for Cortex-A76
Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to the L2 to prevent this.

Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-26 16:21:06 +00:00
Louis Mayencourt 508d71108a Add workaround for errata 1130799 for Cortex-A76
TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to
prevent this.

Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-26 16:21:06 +00:00
Louis Mayencourt 98551591f5 Add workaround for errata 790748 for Cortex-A75
Internal timing conditions might cause the CPU to stop processing
interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this.

Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-26 16:20:59 +00:00
Louis Mayencourt 5f5d1ed7d5 Add workaround for errata 764081 of Cortex-A75
Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.

Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-26 15:53:57 +00:00
Louis Mayencourt e6cab15dc7 Add workaround for errata 855423 of Cortex-A73
Broadcast maintainance operations might not be correctly synchronized
between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this.

Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-26 13:22:56 +00:00
Antonio Niño Díaz 3f995f3078
Merge pull request #1835 from jts-arm/rename
Apply official names to new Arm Neoverse cores
2019-02-22 13:05:37 +00:00
Etienne Carriere c9fe6fed4b ARMv7: support non-LPAE mapping (not xlat_v2)
Support 32bit descriptor MMU table. This is required by ARMv7
architectures that do not support the Large Page Address Extensions.

nonlpae_tables.c source file is dumped from the OP-TEE project:
core_mmu_armv7.c and related header files.

Change-Id: If912d66c374290c49c5a1211ce4c5c27b2d7dc60
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Usama Arif <usama.arif@arm.com>
2019-02-19 17:07:48 +00:00
John Tsichritzis 11088e3924 Rename Cortex-Helios to Neoverse E1
Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 14:02:34 +00:00
John Tsichritzis fd4bb0ad4b Rename Cortex-Helios filenames to Neoverse E1
Change-Id: I33bdb9df0462b056adbd00922b2e73eb720560b3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 14:02:29 +00:00
John Tsichritzis da6d75a0e7 Rename Cortex-Ares to Neoverse N1
Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:50:07 +00:00
John Tsichritzis b04ea14b79 Rename Cortex-Ares filenames to Neoverse N1
Change-Id: I0bb5aca9bb272332340b5baefc473a01f8a27896
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:59 +00:00
Antonio Niño Díaz 873e394b3b
Merge pull request #1810 from antonio-nino-diaz-arm/an/setjmp
Make setjmp/longjmp compliant with the C standard and move them to libc
2019-02-11 09:58:53 +00:00
Antonio Nino Diaz 70b0f2789e libc: Move setjmp to libc folder
Now that setjmp() and longjmp() are compliant with the standard they can
be moved with the other libc files.

Change-Id: Iea3b91c34eb353ace5e171e72f331602d57774d5
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-08 13:42:38 +00:00
Antonio Nino Diaz e056630516 Make setjmp.h prototypes comply with the C standard
Instead of having a custom implementation of setjmp() and longjmp() it
is better to follow the C standard.

The comments in setjmp.h are no longer needed as there are no deviations
from the expected one, so they have been removed.

All SDEI code that relied on them has been fixed to use the new function
prototypes and structs.

Change-Id: I6cd2e21cb5a5bcf81ba12283f2e4c067bd5172ca
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-08 13:42:38 +00:00
Varun Wadekar a1d00bb3ce xlat_tables_v2: mark 'xlat_clean_dcache_range' unused
The armclang compiler can warn if a variable is declared but
is never referenced. The '__attribute__((unused))' attribute
informs the compiler to expect an unused variable, and tells
it not to issue a warning.

This patch marks the 'xlat_clean_dcache_range' function as
"unused" to fix this armclang compiler warning.

Change-Id: I7623f61c2975a01db4d1b80554dd4f9a9e0f7eb6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-02-07 09:01:12 -08:00
Varun Wadekar 596929b971 locks: linker variables to calculate per-cpu bakery lock size
This patch introduces explicit linker variables to mark the start and
end of the per-cpu bakery lock section to help bakery_lock_normal.c
calculate the size of the section. This patch removes the previously
used '__PERCPU_BAKERY_LOCK_SIZE__' linker variable to make the code
uniform across GNU linker and ARM linker.

Change-Id: Ie0c51702cbc0fe8a2076005344a1fcebb48e7cca
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-02-07 09:00:52 -08:00
Varun Wadekar 1242b9a9d0 lib: aarch64: misc_helpers: include bl_common.h
This patch includes bl_common.h to get access to the linker
defined symbols.

Change-Id: I9aa4a6e730273d75a53438854f69971e485bc904
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-02-07 08:47:32 -08:00
Varun Wadekar e095ba34d7 Remove unused function symbols
This patch removes the unused functions that are marked as .global
in code but not defined anywhere in the code.

Change-Id: Ia5057a77c0b0b4a61043eab868734cd3437304cc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-02-07 08:47:21 -08:00
Varun Wadekar bf52f40e2a lib: aarch64: fix non-code symbol errors flagged by armlink
This patch modifies the code to turn __1printf and __2printf into proper
functions to fix the following errors flagged by armlink.

Error: L6318W: backtrace.o(.text.backtrace) contains branch to a non-code symbol __2printf.
Error: L6318W: backtrace.o(.text.backtrace) contains branch to a non-code symbol __2printf.
Error: L6318W: backtrace.o(.text.backtrace) contains branch to a non-code symbol __2printf.
Error: L6318W: backtrace.o(.text.backtrace) contains branch to a non-code symbol __2printf.
Error: L6318W: backtrace.o(.text.backtrace) contains branch to a non-code symbol __2printf.
Error: L6318W: backtrace.o(.text.backtrace) contains branch to a non-code symbol __2printf.

Change-Id: I89126bc2b9db44ce8b8fc9fb1e3fc4c8c60c47a4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-02-07 08:47:09 -08:00
Antonio Nino Diaz 702b600ff3 xlat v2: Fix comment
Change-Id: Id7c22d76b896d1dcac18cdb0e564ce4e02583e33
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-01 12:24:57 +00:00
Sathees Balya cedfa04ba5 lib/xlat_tables: Add support for ARMv8.4-TTST
ARMv8.4-TTST (Small Translation tables) relaxes the lower limit on the
size of translation tables by increasing the maximum permitted value
of the T1SZ and T0SZ fields in TCR_EL1, TCR_EL2, TCR_EL3, VTCR_EL2 and
VSTCR_EL2.

This feature is supported in AArch64 state only.

This patch adds support for this feature to both versions of the
translation tables library. It also removes the static build time
checks for virtual address space size checks to runtime assertions.

Change-Id: I4e8cebc197ec1c2092dc7d307486616786e6c093
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
2019-01-30 11:17:38 +00:00
Antonio Nino Diaz bd9344f670 plat/arm: Sanitise includes
Use full include paths like it is done for common includes.

This cleanup was started in commit d40e0e08283a ("Sanitise includes
across codebase"), but it only cleaned common files and drivers. This
patch does the same to Arm platforms.

Change-Id: If982e6450bbe84dceb56d464e282bcf5d6d9ab9b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-25 16:04:10 +00:00
Paul Beesley 8aabea3358 Correct typographical errors
Corrects typos in core code, documentation files, drivers, Arm
platforms and services.

None of the corrections affect code; changes are limited to comments
and other documentation.

Change-Id: I5c1027b06ef149864f315ccc0ea473e2a16bfd1d
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-01-15 15:16:02 +00:00
Antonio Nino Diaz 2559b2c825 xlat v2: Dynamically detect need for CnP bit
ARMv8.2-TTCNP is mandatory from ARMv8.2 onwards, but it can be implemented
in CPUs that don't implement all mandatory 8.2 features (and so have to
claim to be a lower version).

This patch removes usage of the ARM_ARCH_AT_LEAST() macro and uses system
ID registers to detect whether it is needed to set the bit or not.

Change-Id: I7bcbf0c7c937590dfc2ca668cfd9267c50f7d52c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-11 11:20:10 +00:00