Neoverse N2 erratum 2189731 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR5_EL1[44] to 1 which will cause the CPP instruction to
invalidate the hardware prefetcher state trained from any EL.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Iddc6a59adf9fa3cab560c46f2133e1f5a8b3ad03
Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1[8] to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3
Cortex-A710 erratum 2055002 is a Cat B erratum that applies to
revisions r1p0 & r2p0 and is still open. The workaround is to
set CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r1p0 & r2p0.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I67be1dce53c4651167d8cee33c116e73b9dafe81
Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia1c63fb93a1bdb1c3f4cf019a197b2a59233885a
Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r0p0.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ie92d18a379c66675b5c1c50fd0b8dde130848b21
clang build breaks when both ENABLE_PAUTH (BRANCH_PROTECTOR=1)
and CRASH_REPORTING (DEBUG=1) options are enabled:
include/lib/el3_runtime/cpu_data.h:135:2: error: redefinition of typedef
'assert_cpu_data_crash_stack_offset_mismatch' is a C11 feature [-Werror,
-Wtypedef-redefinition]
assert_cpu_data_crash_stack_offset_mismatch);
^
include/lib/el3_runtime/cpu_data.h:128:2: note: previous definition is here
assert_cpu_data_crash_stack_offset_mismatch);
^
1 error generated.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I22c8c45a94a64620007979d55412dbb57b11b813
Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.
This erratum is avoided by by setting CPUECTLR_EL1[8] to 1.
There is a small performance cost (<0.5%) for setting this
bit.
SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900
Change-Id: I2d72666468b146714a0340ba114ccf0f5165b39c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds the basic CPU library code to support the Demeter
CPU. This CPU is based on the Makalu-ELP core so that CPU lib code
was adapted to create this patch.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib5740b748008a72788c557f0654d8d5e9ec0bb7f
Neoverse V1 erratum 1925756 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the V1 processor core, and it is still open.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I6500dc98da92a7c405b9ae09d794d666e8f4ae52
Neoverse V1 erratum 1852267 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ide5e0bc09371fbc91c2385ffdff74e604beb2dbe
Neoverse V1 erratum 1774420 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I66e27b2518f73faeedd8615a1443a74b6a30f123
If SVE are enabled for both Non-secure and Secure world along with AMU
extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit
from bl31. This restricts access to the AMU register set in normal
world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT
by saving and restoring CPTR_EL3 register from EL3 context.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087
Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic6f92da4d0b995bd04ca5b1673ffeedaebb71d10
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is configured during initial setup and then uses EL3
context save/restore routine to switch between SVE configurations for
different contexts.
Reset value of CPTR_EL3 changed to be most restrictive by default.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and
r1p0 of the A78 processor core, it is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/603e3733492bde1625aa8780
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I71057c4b9625cd9edc1a06946b453cf16ae5ea2c
Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the A77 processor core, it is still open.
SDEN can be found here:
https://documentation-service.arm.com/static/60a63a3c982fc7708ac1c8b1
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib4b963144f880002de308def12744b982d3df868
* changes:
refactor(plat/nvidia): use SOC_ID defines
refactor(plat/mediatek): use SOC_ID defines
refactor(plat/arm): use SOC_ID defines
feat(plat/st): implement platform functions for SMCCC_ARCH_SOC_ID
refactor(plat/st): export functions to get SoC information
feat(smccc): add bit definition for SMCCC_ARCH_SOC_ID
This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to
Cortex A710, Cortex X2, and Cortex A510 respectively.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I056d3114210db71c2840a24562b51caf2546e195
The definitions of SMCCC_ARCH_SOC_ID SoC version return bits are defined
in SMC Calling Convention [1]. Add the masks and shifts for JEP-106 bank
index, JEP-106 identification code, and Implementation defined SoC ID.
Add a macro to easily set JEP-106 fields.
[1] https://developer.arm.com/documentation/den0028/latest/
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iecbd09f6de6728de89dc746d2d1981a5a97a8ab7
Added support for HW computed CRC using Arm ACLE intrinsics.
These are built-in intrinsics available for ARMv8.1-A, and
onwards.
These intrinsics are enabled via '-march=armv8-a+crc' compile
switch for ARMv8-A (supports CRC instructions optionally).
HW CRC support is enabled unconditionally in BL2 for all Arm
platforms.
HW CRC calculation is verified offline to ensure a similar
result as its respective ZLib utility function.
HW CRC calculation support will be used in the upcoming
firmware update patches.
Change-Id: Ia2ae801f62d2003e89a9c3e6d77469b5312614b3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
ELP processors can sometimes have different MIDR values or features so
we are adding the "_arm" suffix to differentiate the reference
implementation from other future versions.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ieea444288587c7c18a397d279ee4b22b7ad79e20
Enable basic support for QEMU "max" CPU.
The "max" CPU does not attampt to emulate any specific CPU, but rather
just enables all the functions emulated by QEMU.
Change-Id: I69c212932ef61433509662d0fefbabb1e9e71cf2
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Since there is a secure and non-secure version of the timer registers
there is no need to preserve their context in EL3.
With that, following registers were removed from EL3 save/restore
routine:
cnthps_ctl_el2
cnthps_tval_el2
cnthps_cval_el2
cnthvs_ctl_el2
cnthvs_tval_el2
cnthvs_cval_el2
cnthp_ctl_el2
cnthp_cval_el2
cnthp_tval_el2
cnthv_ctl_el2
cnthv_cval_el2
cnthv_tval_el2
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I6e2fc09c74a7375c4fccc11f12af4e39e6dc616b
NXP Timer Apis are based on:
- drivers/delay_timer
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cbccf4c082a10affee1143390905b9cc99c3382
ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0. This patch enables support for this
feature in EL3 firmware.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217
The Juno Trusted Entropy Source has a bias, which makes the generated
raw numbers fail a FIPS 140-2 statistic test.
To improve the quality of the numbers, we can use the CPU's CRC
instructions, which do a decent job on conditioning the bits.
This adds a *very* simple version of arm_acle.h, which is typically
provided by the compiler, and contains the CRC instrinsics definitions
we need. We need the original version by using -nostdinc.
Change-Id: I83d3e6902d6a1164aacd5060ac13a38f0057bd1a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.
Also made small changes to fit into TF-A project. Added the source
files to the libc makefile
[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution
Change-Id: I2e94a0b227ec39f6f4530dc50bb477999d27730f
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.
Also made small changes to fit into TF-A project. Added the source
files to the libc makefile
[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution
Change-Id: I9cb581574d46de73c3d6917ebf78935fc5ac075a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.
Also made small changes to fit into TF-A project. Added the source
files to the libc makefile
[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution
Change-Id: I8c3b92751d1ce226c966f7c81fedd83f0846865e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.
Also made small changes to fit into TF-A project. Added the source
files to the libc makefile
[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution
Change-Id: Ica95bf5da722913834fe90bf3fe743aa34e01e80
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
For SoCs which do not implement RAS, use DSB as a barrier to
synchronize pending external aborts at the entry and exit of
exception handlers. This is needed to isolate the SErrors to
appropriate context.
However, this introduces an unintended side effect as discussed
in the https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/3440
A summary of the side effect and a quick workaround is provided as
part of this patch and summarized here:
The explicit DSB at the entry of various exception vectors in BL31
for handling exceptions from lower ELs can inadvertently trigger an
SError exception in EL3 due to pending asyncrhonouus aborts in lower
ELs. This will end up being handled by serror_sp_elx in EL3 which will
ultimately panic and die.
The way to workaround is to update a flag to indicate if the exception
truly came from EL3. This flag is allocated in the cpu_context
structure. This is not a bullet proof solution to the problem at hand
because we assume the instructions following "isb" that help to update
the flag (lines 100-102 & 139-141) execute without causing further
exceptions.
Change-Id: I4d345b07d746a727459435ddd6abb37fda24a9bf
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This workaround
works on revisions r1p0 and r1p1, in r0p0 there is no workaround.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, there is a small performance cost (<0.5%) for setting this bit.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
Enable basic support for Neoverse-N2 CPUs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad