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e10af77b28 Merge pull request #111 'soby-mathew-sm:fix_cookie_to_int_handler' v0.4-rc2 Dan Handley 2014-05-29 17:11:04 +0100
886dfdf21a Merge pull request #115 'athoelke-at:fix-bl31-X1-parameter' Dan Handley 2014-05-29 17:09:24 +0100
bcc8d77933 Merge pull request #114 from 'vikramkanigiri:vk/pass_bl33_args' Dan Handley 2014-05-29 17:05:34 +0100
a378108536 Fix compilation issue for IMF_READ_INTERRUPT_ID build flag Soby Mathew 2014-05-28 17:14:36 +0100
b460b8bf23 Pass 'cookie' parameter to interrupt handler in BL3-1 Soby Mathew 2014-05-27 16:54:31 +0100
0346267194 Allow platform parameter X1 to be passed to BL3-1 Andrew Thoelke 2014-05-28 22:22:55 +0100
f05cb4a764 Pass the args to the BL3-3 entrypoint Vikram Kanigiri 2014-05-28 13:41:51 +0100
05b6edfe26 Merge pull request #110 from soby-mathew:sm/support_normal_irq_in_tsp-v4 into for-v0.4 v0.4-rc1 Dan Handley 2014-05-27 18:46:22 +0100
22e002da5f Merge pull request #112 from danh-arm:dh/refactor-plat-header-v4 into for-v0.4 Dan Handley 2014-05-27 18:34:30 +0100
9865ac1576 Further renames of platform porting functions Dan Handley 2014-05-27 16:17:21 +0100
0ad4691104 Remove FVP specific comments in platform.h Dan Handley 2014-05-27 15:39:41 +0100
10b65ecf47 Fixup Standard SMC Resume Handling Soby Mathew 2014-05-27 10:20:01 +0100
dff8e47a4b Add enable mmu platform porting interfaces for-v0.4-rc0 Dan Handley 2014-05-16 14:08:45 +0100
17a387ad5a Rename FVP specific files and functions Dan Handley 2014-05-15 14:53:30 +0100
dec5e0d1da Move BL porting functions into platform.h Dan Handley 2014-05-15 14:11:36 +0100
5f0cdb059d Split platform.h into separate headers Dan Handley 2014-05-14 17:44:19 +0100
7a9a5f2d22 Remove unused data declarations Dan Handley 2014-05-14 15:13:16 +0100
c6bc071020 Remove extern keyword from function declarations Dan Handley 2014-05-14 12:38:32 +0100
f53d0fce3f Merge pull request #101 from sandrine-bailleux:sb/tf-issue-81-v2 Andrew Thoelke 2014-05-23 12:14:37 +0100
638363eb5f doc: Update information about the memory layout Sandrine Bailleux 2014-05-21 17:08:26 +0100
a37255a205 Make the memory layout more flexible Sandrine Bailleux 2014-05-22 15:28:26 +0100
4f59d8359f Make BL1 RO and RW base addresses configurable Sandrine Bailleux 2014-05-22 15:21:35 +0100
8957fc76aa Merge pull request #104 from athoelke:at/tsp-entrypoints-v2 Andrew Thoelke 2014-05-23 11:00:04 +0100
65335d45f5 Merge pull request #105 from athoelke:sm/support_normal_irq_in_tsp-v2 Andrew Thoelke 2014-05-23 11:00:04 +0100
8545a8744b Merge pull request #102 from achingupta:ag/tf-issues#104-v2 Andrew Thoelke 2014-05-23 11:00:04 +0100
9253530279 Merge pull request #100 from jcastillo-arm:jc/tf-issues/149-v4 Andrew Thoelke 2014-05-23 11:00:04 +0100
659a670132 Merge pull request #101 from sandrine-bailleux:sb/tf-issue-81-v2 Andrew Thoelke 2014-05-23 11:00:04 +0100
b3bcbcf1de Merge pull request #103 from athoelke:dh/tf-issues#68-v3 Andrew Thoelke 2014-05-23 11:00:04 +0100
db0de0eb50 Merge pull request #99 from vikramkanigiri:vk/tf-issues-133_V3 Andrew Thoelke 2014-05-23 11:00:04 +0100
3ea8540d3c Merge pull request #67 from achingupta:ag/psci_standby_bug_fix Andrew Thoelke 2014-05-23 11:00:04 +0100
445fe84f98 Limit BL3-1 read/write access to SRAM Andrew Thoelke 2014-05-22 13:44:47 +0100
399fb08fff Use a vector table for TSP entrypoints Andrew Thoelke 2014-05-20 21:43:27 +0100
239b04fa31 Non-Secure Interrupt support during Standard SMC processing in TSP Soby Mathew 2014-05-09 20:49:17 +0100
1151c82101 Allow BL3-2 platform definitions to be optional Dan Handley 2014-04-15 11:38:38 +0100
a20a81e5b4 Enable secure timer to generate S-EL1 interrupts Achin Gupta 2014-05-09 13:33:42 +0100
b44a4435c9 Add S-EL1 interrupt handling support in the TSPD Achin Gupta 2014-05-09 13:21:31 +0100
57356e9094 Add support for asynchronous FIQ handling in TSP Achin Gupta 2014-05-09 12:17:56 +0100
6cf8902131 Add support for synchronous FIQ handling in TSP Achin Gupta 2014-05-09 11:42:56 +0100
fa9c08b7d1 Use secure timer to generate S-EL1 interrupts Achin Gupta 2014-05-09 12:00:17 +0100
dce74b891e Introduce interrupt handling framework in BL3-1 Achin Gupta 2014-05-09 11:07:09 +0100
dcc1816c91 Introduce platform api to access an ARM GIC Achin Gupta 2014-05-04 19:02:52 +0100
e1333f753f Introduce interrupt registration framework in BL3-1 Achin Gupta 2014-05-09 10:03:15 +0100
c429b5e932 Add context library API to change a bit in SCR_EL3 Achin Gupta 2014-05-04 18:38:28 +0100
3ee8a16402 Rework 'state' field usage in per-cpu TSP context Achin Gupta 2014-05-04 18:23:26 +0100
f860e2cf94 Doc: Add the "Building the Test Secure Payload" section Sandrine Bailleux 2014-05-14 16:45:27 +0100
53514b2909 fvp: Move TSP from Secure DRAM to Secure SRAM Sandrine Bailleux 2014-05-20 17:28:25 +0100
2467f70fde TSP: Let the platform decide which secure memory to use Sandrine Bailleux 2014-05-20 17:22:24 +0100
364daf9320 Reserve some DDR DRAM for secure use on FVP platforms Juan Castillo 2014-05-16 15:33:15 +0100
65e196b759 Add enable mmu platform porting interfaces for-v0.4/05.22 Dan Handley 2014-05-16 14:08:45 +0100
9e9ab9ffc1 Rename FVP specific files and functions Dan Handley 2014-05-15 14:53:30 +0100
bb13656c56 Move BL porting functions into platform.h Dan Handley 2014-05-15 14:11:36 +0100
dbad1bacba Add support for BL3-1 as a reset vector Vikram Kanigiri 2014-04-24 11:02:16 +0100
6871c5d3a2 Rework memory information passing to BL3-x images Vikram Kanigiri 2014-05-16 18:48:12 +0100
4112bfa0c2 Populate BL31 input parameters as per new spec Vikram Kanigiri 2014-04-15 18:08:08 +0100
e2bdbec0bb Split platform.h into separate headers Dan Handley 2014-05-14 17:44:19 +0100
29fb905d5f Rework handover interface between BL stages Vikram Kanigiri 2014-05-15 18:27:15 +0100
23ff9baa7e Introduce macros to manipulate the SPSR Vikram Kanigiri 2014-05-13 14:42:08 +0100
41c3a4fa66 Remove unused data declarations Dan Handley 2014-05-14 15:13:16 +0100
1962c0360e Remove extern keyword from function declarations Dan Handley 2014-05-14 12:38:32 +0100
74f99d24a5 Limit BL3-1 read/write access to SRAM Andrew Thoelke 2014-05-22 13:44:47 +0100
111cb04223 Merge pull request #97 from athoelke:at/tsp-entrypoints Andrew Thoelke 2014-05-22 13:11:05 +0100
3f8a491fe2 Merge pull request #84 from soby-mathew:sm/support_normal_irq_in_tsp Andrew Thoelke 2014-05-22 13:10:31 +0100
69846c1418 Merge pull request #79 from achingupta:ag/tf-issues#104 Andrew Thoelke 2014-05-22 13:01:42 +0100
b1329dc96a Merge pull request #98 from jcastillo-arm:jc/tf-issues/149 Andrew Thoelke 2014-05-22 12:58:41 +0100
e8a0cbd0f5 Merge pull request #87 from sandrine-bailleux:sb/tf-issue-81 Andrew Thoelke 2014-05-22 12:56:38 +0100
ad29e8d40a Merge pull request #95 from danh-arm:dh/tf-issues#68 Andrew Thoelke 2014-05-22 12:55:59 +0100
df9cb6bd65 Merge pull request #96 from vikramkanigiri:vk/tf-issues-133 Andrew Thoelke 2014-05-22 12:54:55 +0100
6b8a852c99 Merge pull request #67 from achingupta:ag/psci_standby_bug_fix Andrew Thoelke 2014-05-22 12:53:12 +0100
1a4f19e36a Merge pull request #91 from linmaonly/lin_dev Andrew Thoelke 2014-05-22 12:31:20 +0100
94574b5ee5 Reserve some DDR DRAM for secure use on FVP platforms Juan Castillo 2014-05-16 15:33:15 +0100
ba9dbd1039 Merge pull request #83 from athoelke/at/tf-issues-126 Andrew Thoelke 2014-05-22 12:30:37 +0100
39f6a68bd1 Merge pull request #85 from hliebel/hl/bl30-doc Andrew Thoelke 2014-05-22 12:28:05 +0100
0a145c9593 Allow BL3-2 platform definitions to be optional Dan Handley 2014-04-15 11:38:38 +0100
f69aa6b23c Use a vector table for TSP entrypoints Andrew Thoelke 2014-05-20 21:43:27 +0100
0a483e25b1 Doc: Add the "Building the Test Secure Payload" section Sandrine Bailleux 2014-05-14 16:45:27 +0100
4b2916fdb6 fvp: Move TSP from Secure DRAM to Secure SRAM Sandrine Bailleux 2014-05-20 17:28:25 +0100
0d15a2290f TSP: Let the platform decide which secure memory to use Sandrine Bailleux 2014-05-20 17:22:24 +0100
d846780e89 Add support for BL3-1 as a reset vector Vikram Kanigiri 2014-04-24 11:02:16 +0100
a0192cc2d7 Rework memory information passing to BL3-x images Vikram Kanigiri 2014-05-16 18:48:12 +0100
0eab2a5889 Populate BL31 input parameters as per new spec Vikram Kanigiri 2014-04-15 18:08:08 +0100
273468af19 Rework handover interface between BL stages Vikram Kanigiri 2014-05-15 18:27:15 +0100
cfd102d6c4 Extend SPSR definitions for full use of ELx modes Vikram Kanigiri 2014-05-13 14:42:08 +0100
034b699c98 Merge pull request #93 from danh-arm:dh/tf-issues#68 for-v0.4/05.21 Andrew Thoelke 2014-05-21 15:10:32 +0100
cdb738cd65 Allow BL3-2 platform definitions to be optional Dan Handley 2014-04-15 11:38:38 +0100
c4cc3af7ae Merge pull request #91 from linmaonly:lin_dev Andrew Thoelke 2014-05-21 11:31:18 +0100
421c572a7e Merge commit 'for-v0.4/05.20^' into for-v0.4 Andrew Thoelke 2014-05-21 11:30:59 +0100
558c76b1c1 Merge pull request #90 from jcastillo-arm:jc/tf-issues/149 Andrew Thoelke 2014-05-21 11:26:05 +0100
041ba7ca1f Doc: Add the "Building the Test Secure Payload" section Sandrine Bailleux 2014-05-14 16:45:27 +0100
b09d732c76 fvp: Move TSP from Secure DRAM to Secure SRAM Sandrine Bailleux 2014-05-20 17:28:25 +0100
2102ef2275 TSP: Let the platform decide which secure memory to use Sandrine Bailleux 2014-05-20 17:22:24 +0100
325026c256 fixup! 4749bdc Andrew Thoelke 2014-05-21 10:15:42 +0100
444281cc41 Address issue 156: 64-bit addresses get truncated Addresses were declared as "unsigned int" in drivers/arm/peripherals/pl011/pl011.h and in function init_xlation_table. Changed to use "unsigned long" instead Fixes ARM-software/tf-issues#156 Lin Ma 2014-05-20 11:25:55 -0700
4749bdc6e7 Add support for BL3-1 as a reset vector Vikram Kanigiri 2014-04-24 11:02:16 +0100
8884e62864 Rework memory information passing to BL3-x images Vikram Kanigiri 2014-05-16 18:48:12 +0100
2d8a691778 Populate BL31 input parameters as per new spec Vikram Kanigiri 2014-04-15 18:08:08 +0100
28e3d2688a Rework handover interface between BL stages Vikram Kanigiri 2014-05-15 18:27:15 +0100
4ac66a7d62 Extend SPSR definitions for full use of ELx modes Vikram Kanigiri 2014-05-13 14:42:08 +0100
bd8da77ac6 Merge pull request #87 from sandrine-bailleux:sb/tf-issue-81 for-v0.4/05.20 Andrew Thoelke 2014-05-20 14:44:57 +0100
f4d25547dc Reserve some DDR DRAM for secure use on FVP platforms Juan Castillo 2014-05-16 15:33:15 +0100
594020f284 Doc: Add the "Building the Test Secure Payload" section Sandrine Bailleux 2014-05-14 16:45:27 +0100