Commit Graph

3532 Commits

Author SHA1 Message Date
Samuel Holland 560581eceb allwinner: Add platform PSCI functions required for SMP
The reset vector entry point is preserved across CPU resets, so it only
needs to be set once at boot.

Hotplugged CPUs are not actually powered down, but are put in a wfi with
the GIC disconnected.

With this commit, Linux is able to enable, hotplug and use all four CPUs.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-06-15 11:45:24 +01:00
Samuel Holland 333d66cf4e allwinner: Add functions to control CPU power/reset
sun50i_cpu_on will be used by the PSCI implementation to initialize
secondary cores for SMP. Unfortunately, sun50i_cpu_off is not usable by
PSCI directly, because it is not possible for a CPU to use this function
to power itself down. Power cannot be shut off until the outputs are
clamped, and MMIO does not work once the outputs are clamped.

But at least CPU0 can shutdown the other cores early in the BL31 boot
process and before shutting down the system.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-06-15 11:45:24 +01:00
Samuel Holland 64b3d9d88e allwinner: Add Allwinner A64 support
The Allwinner A64 SoC is quite popular on single board computers.
It comes with four Cortex-A53 cores in a singe cluster and the usual
peripherals for set-top box/tablet SoC.

The ATF platform target is called "sun50i_a64".

[Andre: adapted to amended directory layout, removed unneeded definitions ]

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-06-15 11:45:24 +01:00
Samuel Holland 58032586f8 allwinner: Introduce basic platform support
This platform supports Allwinner's SoCs with ARMv8 cores. So far they
all sport a single cluster of Cortex-A53 cores.

"sunxi" is the original code name used for this platform, and since it
appears in the Linux kernel and in U-Boot as well, we use it here as a
short file name prefix and for identifiers.

This port includes BL31 support only. U-Boot's SPL takes the role of the
primary loader, also doing the DRAM initialization. It then loads the
rest of the firmware, namely ATF and U-Boot (BL33), then hands execution
over to ATF.

This commit includes the basic platform code shared across all SoCs.
There is no platform.mk yet.

[Andre: moved files into proper directories, supported RESET_TO_BL31,
	various clean ups and simplifications ]

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-06-15 11:45:24 +01:00
Chandni Cherukuri 649b43f82d sgi/mmap: Remove SGI specific MMAP functions
Remove the redundant SGI functions which map memory
for BL1 and BL2.

Change-Id: I651a06d0eb6d28263a56f59701bb3815f1ba93dc
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
2018-06-15 10:17:36 +05:30
Chandni Cherukuri ea3f1be5bd sgi/dyncfg: add system-id node in hw-config dtb
Append a node to hw-config dtb which will include a property to hold
the value of the SSC_VERSION register. This will be used by the BL33
stage to determine the platform-id and the config-id of the platform
it is executing on.

Change-Id: Ie7b1e5d8c1bbe0efdb7ef0714f14b7794ec6058e
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
2018-06-15 10:17:24 +05:30
Chandni Cherukuri 39b66f68d8 sgi/dyncfg: add dts files to enable support for dynamic config
Remove the existing method of populating the platform id in arg2 of
BL33 which is no longer needed with dynamic configuration feature
enabled as the BL33 will get this information directly via the config
files. Add the tb_fw_config and hw_config dts files.

Change-Id: I3c93fec2aedf9ef1f774a5f0969d2d024e47ed2c
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
2018-06-15 10:17:11 +05:30
Yann Gautier 167c5f8098 utils: Add BIT_32 and BIT_64 macros
When applying some MISRA rules, lots of issues are raised with BIT macro
on AARCH32, and cast on uint32_t would be required (Rule 10.3).
The macros BIT_32 and BIT_64 are then created for 32bit and 64bit.
Then the BIT macro defaults on BIT_64 on AARCH64,
and on BIT_32 on AARCH32.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
2018-06-14 18:35:38 +02:00
Yann Gautier 39676357af Add GENMASK macros
Import GENMASK_32 and GENMASK_64 macros from optee-os (permissive license).
And default GENMASK is set to GENMASK_32 for AARCH32,
and to GENMASK_64 for 64bit arch.

fixes arm-software/tf-issues#596

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2018-06-14 18:35:33 +02:00
Roberto Vargas 033648652f Make TF UUID RFC 4122 compliant
RFC4122 defines that fields are stored in network order (big endian),
but TF-A stores them in machine order (little endian by default in TF-A).
We cannot change the future UUIDs that are already generated, but we can store
all the bytes using arrays and modify fiptool to generate the UUIDs with
the correct byte order.

Change-Id: I97be2d3168d91f4dee7ccfafc533ea55ff33e46f
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-06-14 14:41:00 +01:00
Dimitris Papastamos 1ebdbe79c7
Merge pull request #1414 from antonio-nino-diaz-arm/an/fix-rpi3-doc
rpi3: Fix kernel boot documentation
2018-06-14 14:40:24 +01:00
Dimitris Papastamos 498161a504
Merge pull request #1419 from danielboulby-arm/db/docs
Correct ordering of log levels in documentation
2018-06-14 14:35:17 +01:00
Dimitris Papastamos 4a410a3ba3
Merge pull request #1417 from paulkocialkowski/integration
rockchip: Move stdint header to the offending header file
2018-06-14 14:34:46 +01:00
Dimitris Papastamos 59c4346383
Merge pull request #1415 from antonio-nino-diaz-arm/an/spm-fixes
Minor fixes to SPM
2018-06-14 14:33:13 +01:00
Dimitris Papastamos f3a5e3d6ec
Merge pull request #1412 from masahir0y/uniphier
uniphier: fix CCI-500 connection for LD20
2018-06-14 14:32:41 +01:00
Yann Gautier 75df62699b xlat_v2: add a check on mm_cursor->size to avoid infinite loop
The issue can occur if end_va is equal to the max architecture address,
and when mm_cursor point to the last entry of mmap_region_t table: {0}.
The first line of the while will then be true, e.g. on AARCH32, we have:
mm_cursor->base_va (=0) + mm_cursor->size (=0) - 1 == end_va (=0xFFFFFFFF)
And the mm_cursor->size = 0 will be lesser than mm->size

A check on mm_cursor->size != 0 should be done as in the previous while,
to avoid such kind of infinite loop.

fixes arm-software/tf-issues#594

Signed-off-by: Yann Gautier <yann.gautier@st.com>
2018-06-14 14:36:20 +02:00
Daniel Boulby 9bd5a4ce1e Correct ordering of log levels in documentation
Changed the ordering of the log levels in the documentation to
mate the code

Change-Id: Ief1930b73d833fdf675b039c98046591c0c264c1
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-06-14 10:27:03 +01:00
Paul Kocialkowski fb83888b61 rockchip: Move stdint header to the offending header file
The stdint header was introduced to rk3399's plat_sip_calls.c in order
to fix missing stdint definitions. However, ordering headers
alphabetically caused the fix to be ineffective, as stint was then
included after the offending header file (dfs.h).

Move the stdint include to that header to properly fix the issue.

Change-Id: Ieaad37a7932786971488ab58fc5b169bfa79e197
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2018-06-13 20:37:50 +02:00
Antonio Nino Diaz 2d8f831fb2 rpi3: Fix kernel boot documentation
The order of the arguments of memmap was swapped. The old command was
reserving 256 MiB from the 16 MiB barrier, it should be reserving only
16 MiB at the 256 MiB barrier.

It worked because the memory used by the Trusted Firmware was reserved
anyway.

Change-Id: I3fefcfc0105ecf05ba5606517bc3236f4eb24ceb
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-06-13 15:05:53 +01:00
Dimitris Papastamos ed4cf49020
Merge pull request #1402 from glneo/for-upstream-uart
drivers: ti: uart: Add TI specific 16550 initialization
2018-06-13 14:19:53 +01:00
Dimitris Papastamos 74a44dca29
Merge pull request #1399 from danielboulby-arm/db/MISRA
MISRA 5.1, 5.3 & 5.7 compliance changes
2018-06-13 13:32:14 +01:00
Sandrine Bailleux d801a1d035 SPM: Treat SP xlat tables the same as others
The translation tables allocated for the Secure Partition do not need
to be treated as a special case. They can be put amongst the other
tables mapping BL31's general purpose memory. They will be mapped with
the same attributes as them, which is fine.

The explicit alignment constraint in BL31's linker script to pad the
last page of memory allocated to the Secure Partition's translation
tables is useless too, as page tables are per se pages, thus their
end address is naturally aligned on a page-boundary.

In fact, this patch does not change the existing behaviour. Since
patch 22282bb68a ("SPM: Move all SP-related info to SP context
struct"), the secure_partition.c file has been renamed into sp_xlat.c
but the linker script has not been properly updated. As a result, the
SP translation tables are not specifically put at the start of the
xlat_table linker section, the __SP_IMAGE_XLAT_TABLES_START__/_END__
symbols have the same value, the size of the resulting mmap_region
covering these xlat tables is 0 and so it is ignored.

Change-Id: I4cf0a4cc090298811cca53fc9cee74df0f2b1512
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-06-13 09:19:41 +01:00
Antonio Nino Diaz a0b9bb79a0 xlat v2: Introduce xlat granule size helpers
The function xlat_arch_is_granule_size_supported() can be used to check
if a specific granule size is supported. In Armv8, AArch32 only supports
4 KiB pages. AArch64 supports 4 KiB, 16 KiB or 64 KiB depending on the
implementation, which is detected at runtime.

The function xlat_arch_get_max_supported_granule_size() returns the max
granule size supported by the implementation.

Even though right now they are only used by SPM, they may be useful in
other places in the future. This patch moves the code currently in SPM
to the xlat tables lib so that it can be reused.

Change-Id: If54624a5ecf20b9b9b7f38861b56383a03bbc8a4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-06-13 09:19:41 +01:00
Antonio Nino Diaz 83a393ba3e SPM: Initialize SP args as expected by cm library
In the context management library, cm_setup_context() takes the
information in ep_info to fill the registers x0-x7. This patch replaces
the current code that sets them manually by the correct initialization
code.

Change-Id: Id1fdf4681b154026c2e3af1f9b05b19582b7d16d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-06-13 09:19:41 +01:00
Antonio Nino Diaz f13cb561f0 LOAD_IMAGE_V1: Align BL2 memory layout struct to 8 bytes
In LOAD_IMAGE_V1 (i.e when LOAD_IMAGE_V2=0) the bl2_tzram_layout is,
by default, assigned to the bl1_tzram_layout->free_base which is
dynamically calculated based on the images loaded in memory. There is a
chance that the bl2_tzram_layout will be assigned a value not aligned to
8 bytes. This patch rounds up the free_base value for the required
alignment.

This doesn't happen in LOAD_IMAGE_V2 because the bl2_tzram_layout is
assigned by default to the bl1_tzram_layout->total_base, which is
aligned.

Change-Id: Idc583e7dad993d02ac6791797406118c96f83fa1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-06-12 14:08:48 +01:00
Daniel Boulby 776ff52a8d Fix MISRA Rule 5.7 Part 3
Rule 5.7: A tag name shall be a unique identifier

Follow convention of shorter names for smaller scope to fix
violations of MISRA rule 5.7

Fixed For:
    make ARM_TSP_RAM_LOCATION=tdram LOG_LEVEL=50 PLAT=fvp SPD=opteed

Change-Id: I5fbb5d6ebddf169550eddb07ed880f5c8076bb76
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-06-12 13:21:36 +01:00
Daniel Boulby a138f76871 Fix MISRA Rule 5.7 Part 2
Follow convention of shorter names for smaller scope to fix
violations of MISRA rule 5.7

To prevent violation of directive 4.5 having variable name channel
in css_pm_scmi.c not being typographically ambiguous change macro
argument CHANNEL in css_mhu_doorbell.h change argument to _channel
to fit with our convention which is a permitted exception of
directive 4.5 for this project

Rule 5.7: A tag name shall be a unique identifier

Fixed for:
    make LOG_LEVEL=50 PLAT=juno

Change-Id: I147cdb13553e83ed7df19149b282706db115d612
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-06-12 13:21:36 +01:00
Daniel Boulby 4069292388 Fix MISRA Rule 5.7 Part 1
Rule 5.7: A tag name shall be a unique identifier

There were 2 amu_ctx struct type definitions:
    - In lib/extensions/amu/aarch64/amu.c
    - In lib/cpus/aarch64/cpuamu.c

Renamed the latter to cpuamu_ctx to avoid this name clash

To avoid violation of Rule 8.3 also change name of function
amu_ctxs to unique name (cpuamu_ctxs) since it now returns a
different type (cpuamu_ctx) than the other amu_ctxs function

Fixed for:
    make LOG_LEVEL=50 PLAT=fvp

Change-Id: Ieeb7e390ec2900fd8b775bef312eda93804a43ed
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-06-12 13:21:36 +01:00
Daniel Boulby ff4e86f90e Fix MISRA Rule 5.3 Part 5
Use a _ prefix for macro arguments to prevent that argument from
hiding variables of the same name in the outer scope

Rule 5.3: An identifier declared in an inner scope shall not
          hide an identifier declared in an outer scope

Fixed For:
    make LOG_LEVEL=50 PLAT=juno

Change-Id: I575fbc96e8267f2b075e88def1f6e3185394613a
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-06-12 13:21:36 +01:00
Daniel Boulby 7cb81945d5 Fix MISRA Rule 5.3 Part 4
Use a _ prefix for macro arguments to prevent that argument from
hiding variables of the same name in the outer scope

Rule 5.3: An identifier declared in an inner scope shall not
          hide an identifier declared in an outer scope

Fixed For:
    make PLAT=fvp USE_COHERENT_MEM=0

Change-Id: If50c583d3b63799ee6852626b15be00c0f6b10a0
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-06-12 13:21:36 +01:00
Daniel Boulby 7c934242e3 Fix MISRA Rule 5.3 Part 3
Use a _ prefix for macro arguments to prevent that argument from
hiding variables of the same name in the outer scope

Rule 5.3: An identifier declared in an inner scope shall not
          hide an identifier declared in an outer scope

Fixed For:
    make PLAT=fvp SPD=tspd

Change-Id: I2d711b9584c4cb9ba3814ecd2ca65a42b7e24179
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-06-12 13:21:36 +01:00
Daniel Boulby 896a5902ec Fix MISRA Rule 5.3 Part 2
Use a _ prefix for Macro arguments to prevent that argument from
hiding variables of the same name in the outer scope

Rule 5.3: An identifier declared in an inner scope shall not
          hide an identifier declared in an outer scope

Fixed For:
    make LOG_LEVEL=50 PLAT=fvp

Change-Id: I67b6b05cbad4aeca65ce52981b4679b340604708
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-06-12 13:21:36 +01:00
Daniel Boulby d3775d46a4 Fix MISRA Rule 5.3 Part 1
Conflict with function name and variable name within that function.
Change the name of the function from image_size to get_image_size
to remove conflict and make the function fit the normal project
naming convention.

Rule 5.3:  An identifier declared in an inner scope shall not
           hide an identifier declared in an outer scope

Fixed For:
    make LOG_LEVEL=50 PLAT=fvp

Change-Id: I1a63d2730113e2741fffa79730459c584b0224d7
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-06-12 13:21:36 +01:00
Daniel Boulby 87d3aacc88 Fix MISRA Rule 5.1
Rule 5.1: External identifiers shall be distinct

Some of the identifier names in the GICv3 driver were so long that the
first 31 characters were identical. This patch shortens these names to
make sure they are different.

Fixed for:
    LOG_LEVEL=50 PLAT=fvp

Change-Id: Iecd551e3a015d144716b87b42c83dd3ab8c34d90
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-06-12 13:21:36 +01:00
Dimitris Papastamos e109b0ffea
Merge pull request #1391 from jts-arm/misra
MISRA rule 21.15 fix
2018-06-12 13:01:35 +01:00
Satoshi Ikawa 4fc1a38185 uniphier: fix CCI-500 connection for LD20
The slave ports of LD20 CCI-500 are connected as follows:

  S0: CA53
  S1: CA72

Be careful because the slave interface is not arranged in the
cluster number order (CA72: cluster 0, CA53: cluster 1).

Root-caused-by: Tetsuya Yoshizaki <yoshizaki.tetsuya@socionext.com>
Signed-off-by: Satoshi Ikawa <ikawa.satoshi@socionext.com>
2018-06-12 10:38:20 +09:00
Benjamin Fair 529b541e8b drivers: ti: uart: Add TI specific 16550 initialization
On TI platforms the UART is disabled by default and must be explicitly
enabled using the MDR1 register.

NOTE: The original definition of
http://www.ti.com/lit/ds/symlink/pc16550d.pdf has no MDR register, but
many TI SoCs implementing 16550 do have a quirky MDR register
implemented. So, this should be enabled with TI_16550_MDR_QUIRK

NOTE: In such implementation, the CSR register does not exist.

Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-06-11 14:26:32 -05:00
Dimitris Papastamos 42be6fc57e Adjust BL2_AT_EL3 memory layout
For the BL2_AT_EL3 configuration, move BL2 higher up to make more
space for BL31.  Adjust the BL31 limit to be up to BL2 base.  This is
because BL2 is always resident for the BL2_AT_EL3 configuration and
thus we cannot overlay it with BL31.

Change-Id: I71e89863ed48f5159e8b619f49c7c73b253397aa
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-06-11 14:18:06 +01:00
John Tsichritzis bdcd33a858 MISRA rule 21.15 fix
Rule 21.15: The pointer arguments to the Standard Library functions
    memcpy, memmove and memcmp shall be pointers to qualified or unqualified
    versions of compatible types.

    Basically that means that both pointer arguments must be of the same
    type. However, even if the pointers passed as arguments to the above
    functions are of the same type, Coverity still thinks it's a violation
    if we do pointer arithmetics directly at the function call. Thus the
    pointer arithmetic operations were moved outside of the function
    argument.

    First detected on the following configuration
            make PLAT=fvp LOG_LEVEL=50

    Change-Id: I8b912ec1bfa6f2d60857cb1bd453981fd7001b94
    Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-06-11 11:41:09 +01:00
Dimitris Papastamos 608529aa24
Merge pull request #1397 from dp-arm/dp/cortex-a76
Add support for Cortex-A76 and Cortex-Ares
2018-06-08 14:01:38 +01:00
Dimitris Papastamos 11bebd7cab
Merge pull request #1409 from ARM-software/revert-1389-db/bugfix
Revert "Code change to fix small bugs"
2018-06-08 13:17:47 +01:00
Dimitris Papastamos 4a581b061c
Revert "Code change to fix small bugs" 2018-06-08 13:17:26 +01:00
Dimitris Papastamos 31ece1e025
Merge pull request #1405 from dp-arm/dp/cve_2017_5715
Fast path SMCCC_ARCH_WORKAROUND_1 calls from AArch32
2018-06-08 11:47:13 +01:00
Dimitris Papastamos 6f03bc7753 SDEI: Ensure SDEI handler executes with CVE-2018-3639 mitigation enabled
When dynamic mitigation is used, the SDEI handler is required to
execute with the mitigation enabled by default, regardless of the
mitigation state for lower ELs.  This means that if the kernel or
hypervisor explicitly disables the mitigation and then later when the
event is dispatched, the dispatcher will remember the mitigation state
for the lower ELs but force the mitigation to be on during the SDEI
handler execution.  When the SDEI handler returns, it will restore the
mitigation state.

This behaviour is described in "Firmware interfaces for mitigating
cache speculation vulnerabilities System Software on Arm Systems"[0].

[0] https://developer.arm.com/cache-speculation-vulnerability-firmware-specification

Change-Id: I8dd60b736be0aa9e832b0f92d67a401fdeb417f4
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-06-08 11:46:31 +01:00
Dimitris Papastamos d6b798097e Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76
The Cortex-A76 implements SMCCC_ARCH_WORKAROUND_2 as defined in
"Firmware interfaces for mitigating cache speculation vulnerabilities
System Software on Arm Systems"[0].

Dynamic mitigation for CVE-2018-3639 is enabled/disabled by
setting/clearning bit 16 (Disable load pass store) of `CPUACTLR2_EL1`.

NOTE: The generic code that implements dynamic mitigation does not
currently implement the expected semantics when dispatching an SDEI
event to a lower EL.  This will be fixed in a separate patch.

[0] https://developer.arm.com/cache-speculation-vulnerability-firmware-specification

Change-Id: I8fb2862b9ab24d55a0e9693e48e8be4df32afb5a
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-06-08 11:46:31 +01:00
Dimitris Papastamos ee7cda31c7 Set DYNAMIC_WORKAROUND_CVE_2018_3639=1 on FVP by default
The upcoming patch that adds dynamic mitigation for Cortex-A76
requires that DYNAMIC_WORKAROUND_CVE_2018_3639=1.  On FVP, we pull in
all the CPU files into the build which means there will be a build
failure if DYNAMIC_WORKAROUND_CVE_2018_3639=0.

Change-Id: I2e781cbeafbf5d16eaabf76a1677e0c9f81269d2
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-06-08 11:46:31 +01:00
Dimitris Papastamos 040b546e94 Implement Cortex-Ares 1043202 erratum workaround
The workaround uses the instruction patching feature of the Ares cpu.

Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-06-08 11:46:31 +01:00
Dimitris Papastamos 08268e27ab Add AMU support for Cortex-Ares
Change-Id: Ia170c12d3929a616ba80eb7645c301066641f5cc
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-06-08 11:46:31 +01:00
Isla Mitchell abbffe98ed Add support for Cortex-Ares and Cortex-A76 CPUs
Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit
(DSU).  The power-down and power-up sequences are therefore mostly
managed in hardware, and required software operations are simple.

Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2018-06-08 11:46:31 +01:00
Dimitris Papastamos 83685de911
Merge pull request #1389 from danielboulby-arm/db/bugfix
Code change to fix small bugs
2018-06-08 11:45:06 +01:00