Commit Graph

8067 Commits

Author SHA1 Message Date
Varun Wadekar 64b2a237aa Tegra: spe: do not flush console in console_putc
SPE no longer requires the flush bit to be set to start transmitting
characters over the physical uart. Therefore, the flush bit is no
longer required when calling console_core_putc. However, flushing the
console still requires the flush bit.

This patch removes the flush bit from the mailbox messages in
console_core_putc to improve ACK latency.

Original change by: Mustafa Bilgen <mbilgen@nvidia.com>

Change-Id: I5b7d1f3ea69ea2ce308566dbaae222b04e4c373d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-08-24 21:26:40 +00:00
kalyanic fbcd053cb4 Tegra: verify platform compatibility
This patch verifies that the binary image is compatible with
chip ID of the platform.

Change-Id: I28db221b4442aa8827a092faadf32f110d7c5cb4
Signed-off-by: kalyanic <kalyanic@nvidia.com>
2020-08-24 21:26:32 +00:00
Madhukar Pappireddy 2b4103f786 Merge "tools: Get the tool's binary name from the main makefile" into integration 2020-08-24 17:04:33 +00:00
Manish Pandey 6f3ee4a8ad Merge "SPMD: Dont forward PARTITION_INFO_GET from secure FF-A instance" into integration 2020-08-24 11:45:14 +00:00
Sayanta Pattanayak 0df3eb70ff n1sdp: remote chip SPI numbering for multichip GIC routing
Allocated 512-959 SPI numbers for remote n1sdp chip and same has been
referenced for GIC routing table.

Change-Id: Id79ea493fd665ed93fe9644a59e363ec10441098
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
2020-08-24 15:47:09 +05:30
Manish V Badarkhe fafd3ec9c9 tools: Get the tool's binary name from the main makefile
Currently, the tool's makefile override the tool's binary name
which is already been defined in the main makefile.
Hence fix is provided so that the tool's makefile get the tool's
binary name from the main makefile instead of overriding it.

Change-Id: I8af2bd391a96bba2dbcddef711338a94ebf5f038
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-08-23 05:41:13 +01:00
Mark Dykes 8d0a3bb38d Merge "Revert "libc/memset: Implement function in assembler"" into integration 2020-08-21 19:44:05 +00:00
Mark Dykes f5402ef7a8 Revert "libc/memset: Implement function in assembler"
This reverts commit e7d344de01.
 This reverts the patch https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5313 due to a timing issue with the merge.  The merge occurred at the same time as the additional comments and thusly were were not seen until the merge was done.  This reverts the change and additional patches from Alexei will follow to address the concerns expressed in the orignal patch.

Change-Id: Iae5f6403c93ac13ceeda29463883fcd4c437f2b7
2020-08-21 19:33:46 +00:00
Ruari Phipps 545b8eb33e SPMD: Dont forward PARTITION_INFO_GET from secure FF-A instance
Signed-off-by: Ruari Phipps <ruari.phipps@arm.com>
Change-Id: I4e9fbfcfda4ed4b87d5ece1c609c57c73d617d4c
2020-08-21 14:21:51 +00:00
Olivier Deprez a6ab1ae39c Merge changes from topic "spm-secondary-cores" into integration
* changes:
  SPMC: embed secondary core ep info into to SPMC context
  SPMC: manifest changes to support multicore boot
  SPMD: secondary cores PM on and off SPD hooks relayed to SPMC
  SPMD: handle SPMC message to register secondary core entry point
  SPMD: introduce SPMC to SPMD messages
  SPMD: register the SPD PM hooks
  SPMD: add generic SPD PM handlers
  SPMD: enhance SPMC internal boot states
  SPMD: entry point info get helper
2020-08-21 14:18:57 +00:00
Sandrine Bailleux 768f83310e Merge "doc: Minor formatting improvement in the coding guidelines document" into integration 2020-08-21 12:14:51 +00:00
Olivier Deprez 02d50bb018 SPMC: embed secondary core ep info into to SPMC context
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Icdb15b8664fb3467ffd55b44d1f0660457192586
2020-08-20 18:06:06 +01:00
Olivier Deprez 2111b0024c SPMC: manifest changes to support multicore boot
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Icf90c2ccce75257908ba3d4703926041d64b1dd3
2020-08-20 18:06:06 +01:00
Olivier Deprez a92bc73b8e SPMD: secondary cores PM on and off SPD hooks relayed to SPMC
Define SPMD PM hooks for warm boot and off events. svc_on_finish handler
enters the SPMC at the entry point defined by the secondary EP register
service. The svc_off handler notifies the SPMC that a physical core is
being turned off through a notification message.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I2609a75a0c6ffb9f6313fc09553be2b29a41de59
2020-08-20 18:06:06 +01:00
Olivier Deprez f0d743dbcd SPMD: handle SPMC message to register secondary core entry point
Upon booting, the SPMC running on the primary core shall register the
secondary core entry points to which a given secondary core being woken
up shall jump to into the SPMC . The current implementation assumes the
SPMC calls a registering service implemented in the SPMD for each core
identified by its MPIDR. This can typically happen in a simple loop
implemented in the early SPMC initialization routines by passing each
core identifier associated with an entry point address and context
information.
This service is implemented on top of a more generic SPMC<=>SPMD
interface using direct request/response message passing as defined by
the FF-A specification.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I1f70163b6b5cee0880bd2004e1fec41e3780ba35
2020-08-20 18:06:06 +01:00
Olivier Deprez c2901419b5 SPMD: introduce SPMC to SPMD messages
FF-A interface to handle SPMC to SPMD direct messages requests.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Ia707a308c55561a31dcfa86e554ea1c9e23f862a
2020-08-20 18:06:06 +01:00
Olivier Deprez a334c4e691 SPMD: register the SPD PM hooks
Change-Id: If88d64c0e3d60accd2638a55f9f3299ec700a8c8
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
2020-08-20 18:06:06 +01:00
Olivier Deprez b058f20a7e SPMD: add generic SPD PM handlers
This patch defines and registers the SPMD PM handler hooks.
This is intended to relay boot and PM events to the SPMC.

Change-Id: If5a758d22b8d2152cbbb83a0cad563b5e1c6bd49
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
2020-08-20 18:06:06 +01:00
Olivier Deprez 9dcf63dd8b SPMD: enhance SPMC internal boot states
This patch adds SPMC states used by the SPMD to track SPMC boot phases
specifically on secondary cores.

Change-Id: If97af7352dda7f04a8e46a56892a2aeddcfab91b
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
2020-08-20 18:06:06 +01:00
Olivier Deprez c0267cc994 SPMD: entry point info get helper
This patch provides a helper to get the entry_point_info
structure used by the boot CPU as it is used to initialise
the SPMC context on secondary CPUs.

Change-Id: I99087dc7a86a7258e545d24a2ff06aa25170f00c
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
2020-08-20 18:06:06 +01:00
Sandrine Bailleux 06ffa16694 doc: Recommend using C rather than assembly language
Add a section for that in the coding guidelines.

Change-Id: Ie6819c4df5889a861460eb96acf2bc9c0cfb494e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-08-20 15:29:01 +00:00
Manish Pandey 1566bc3e53 Merge "plat: imx8m: Fix the race condition during cpu hotplug" into integration 2020-08-20 15:07:13 +00:00
Olivier Deprez 7638011146 Merge changes from topic "at_errata_fix" into integration
* changes:
  doc: Update description for AT speculative workaround
  lib/cpus: Report AT speculative erratum workaround
  Add wrapper for AT instruction
2020-08-20 14:40:06 +00:00
Jacky Bai fe5e1c145a plat: imx8m: Fix the race condition during cpu hotplug
CPU hotplug & cpuidle have some race condition when doing CPU hotplug
stress test. different CPU cores have the chance to access the same
GPC register(A53_AD), so lock is necessary to do exlusive access.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I1296592e05fa78429c3f0fac066951521db755e3
2020-08-20 14:23:19 +00:00
Manish Pandey 15e54af35d Merge "SPM: Add third cactus partition to manifests" into integration 2020-08-20 09:57:07 +00:00
Sandrine Bailleux 9061c0c9ab doc: Minor formatting improvement in the coding guidelines document
Change-Id: I5362780db422772fd547dc8e68e459109edccdd0
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-08-20 10:41:36 +02:00
André Przywara e168b66d87 Merge changes from topic "aw_drivevbus" into integration
* changes:
  plat/allwinner: Only enable DRIVEVBUS if really needed
  plat/allwinner: Use common gicv2.mk
2020-08-19 22:29:58 +00:00
Mark Dykes e5c84ca63c Merge "libc/memset: Implement function in assembler" into integration 2020-08-19 18:53:55 +00:00
Alexei Fedorov e7d344de01 libc/memset: Implement function in assembler
Trace analysis of FVP_Base_AEMv8A model running in
Aarch32 mode with the build options listed below:
TRUSTED_BOARD_BOOT=1 GENERATE_COT=1
ARM_ROTPK_LOCATION=devel_ecdsa KEY_ALG=ecdsa
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
shows that when auth_signature() gets called
71.84% of CPU execution time is spent in memset() function
written in C using single byte write operations,
see lib\libc\memset.c.
This patch replaces C memset() implementation with assembler
version giving the following results:
- for Aarch32 in auth_signature() call memset() CPU time
reduced to 24.84%.
- Number of CPU instructions executed during TF-A
boot stage before start of BL33 in RELEASE builds:
----------------------------------------------
|  Arch   |     C      |  assembler |    %   |
----------------------------------------------
| Aarch32 | 2073275460 | 1487400003 | -28.25 |
| Aarch64 | 2056807158 | 1244898303 | -39.47 |
----------------------------------------------
The patch also replaces memset.c with aarch64/memset.S
in plat\nvidia\tegra\platform.mk.

Change-Id: Ifbf085a2f577a25491e2d28446ee95a4ac891597
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-08-19 18:21:39 +00:00
Manish Pandey e268ea271a Merge "SPM: Change condition on saving/restoring EL2 registers" into integration 2020-08-19 15:34:50 +00:00
Ruari Phipps 9de91c7542 SPM: Add third cactus partition to manifests
Add information about the third partition so it can be loaded into SPM
when running the tests

Signed-off-by: Ruari Phipps <ruari.phipps@arm.com>
Change-Id: I5544e88df391ef294ddf6b5750d468d3e74892b1
2020-08-19 15:18:54 +00:00
Ruari Phipps 6b704da34b SPM: Change condition on saving/restoring EL2 registers
Make this more scalable by explicitly checking internal and hardware
states at run_time

Signed-off-by: Ruari Phipps <ruari.phipps@arm.com>
Change-Id: I1c6ed1c1badb3538a93bff3ac5b5189b59cccfa1
2020-08-19 15:17:31 +00:00
Manish Pandey 572dea8534 Merge "plat: qti: Fix build failure" into integration 2020-08-19 11:44:55 +00:00
Manish Pandey a3b500449b Merge changes Ic701675c,Ie55e25c8 into integration
* changes:
  plat: imx8m: Correct the imr mask reg offset
  plat: imx8m: Keep A53 PLAT on in wait mode(ret)
2020-08-19 11:27:58 +00:00
Jacky Bai fb9212be17 plat: imx8m: Correct the imr mask reg offset
The number of gpc imr mask reg & the offset is different
on some SOC, so correct it & replace the magic number with
macro define.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ic701675cdd92e043dcd7f06722f2e871068aec74
2020-08-19 09:46:11 +00:00
Jacky Bai 9eb1bb63e1 plat: imx8m: Keep A53 PLAT on in wait mode(ret)
Keep A53 PLAT(SCU) power domain on in wait mode(ret).
RBC count only need to be set in PLAT OFF mode, so
change it accordingly.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ie55e25c8210d298506fc4dca7a9653583db45e0c
2020-08-19 09:46:05 +00:00
Manish Pandey 9ce37110f5 Merge "qemu/qemu_sbsa: enable SPM support" into integration 2020-08-19 09:38:19 +00:00
Manish Pandey 38294532db Merge changes from topic "tegra-downstream-07092020" into integration
* changes:
  Tegra: platform: add function to check t194 chip
  Tegra: common: make plat_psci_ops routines static
2020-08-19 09:37:38 +00:00
Abdul Halim, Muhammad Hadi Asyrafi 5a32a03332 intel: platform: Include GICv2 makefile
This patch update each Intel's platform makefiles to include GICv2
makefile instead of manually sourcing individual c files. This aligns
with latest changes from commit #1322dc94f7.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib1f446a6fc578f73a9ef86f9708ddf12d7d75f48
2020-08-19 14:50:08 +08:00
David Pu 43d22073d4 Tegra: platform: add function to check t194 chip
This patch adds tegra_chipid_is_t194() function to check if it is a
Tegra 194 chip.

Change-Id: I6da6d3a2c9676b748931e42fde1b174cbcb4fd40
Signed-off-by: David Pu <dpu@nvidia.com>
2020-08-18 22:59:05 +00:00
David Pu 57e92daf76 Tegra: common: make plat_psci_ops routines static
This patch makes Tegra platform psci ops routines to static. These
routines are called by PSCI framework and no external linkage is
necessary. This patch also fixes MISRA C-2012 Rule 8.6 violations.

Change-Id: Idd2381809f76dc0fd578c1c92c0f8eea124f2e88
Signed-off-by: David Pu <dpu@nvidia.com>
2020-08-18 22:58:54 +00:00
Masahisa Kojima 6a2426a94f qemu/qemu_sbsa: enable SPM support
Enable the spm_mm framework for the qemu_sbsa platform.
Memory layout required for spm_mm is created in secure SRAM.

Co-developed-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a
2020-08-18 22:45:35 +00:00
Alexei Fedorov 3ee8e4d8de Merge "runtime_exceptions: Update AT speculative workaround" into integration 2020-08-18 16:53:25 +00:00
Alexei Fedorov faf7713c4e Merge "el3_runtime: Rearrange context offset of EL1 sys registers" into integration 2020-08-18 16:53:04 +00:00
Alexei Fedorov e4ded0c69e Merge "el3_runtime: Update context save and restore routines for EL1 and EL2" into integration 2020-08-18 16:50:23 +00:00
Manish Pandey 6b76d1e94e Merge changes from topic "soc-id" into integration
* changes:
  plat/arm: juno: Implement methods to retrieve soc-id information
  plat/arm: fvp: Implement methods to retrieve soc-id information
  plat/arm: remove common code for soc-id feature
2020-08-18 11:02:15 +00:00
Manish V Badarkhe e008a29a18 doc: Update description for AT speculative workaround
Documented the CPU specific build macros created for AT
speculative workaround.

Updated the description of 'ERRATA_SPECULATIVE_AT' errata
workaround option.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ie46a80d4e8183c1d5c8b153f08742a04d41a2af2
2020-08-18 10:49:27 +01:00
Manish V Badarkhe 3b8456bd1c runtime_exceptions: Update AT speculative workaround
As per latest mailing communication [1], we decided to
update AT speculative workaround implementation in order to
disable page table walk for lower ELs(EL1 or EL0) immediately
after context switching to EL3 from lower ELs.

Previous implementation of AT speculative workaround is available
here: 45aecff00

AT speculative workaround is updated as below:
1. Avoid saving and restoring of SCTLR and TCR registers for EL1
   in context save and restore routine respectively.
2. On EL3 entry, save SCTLR and TCR registers for EL1.
3. On EL3 entry, update EL1 system registers to disable stage 1
   page table walk for lower ELs (EL1 and EL0) and enable EL1
   MMU.
4. On EL3 exit, restore SCTLR and TCR registers for EL1 which
   are saved in step 2.

[1]:
https://lists.trustedfirmware.org/pipermail/tf-a/2020-July/000586.html

Change-Id: Iee8de16f81dc970a8f492726f2ddd57e7bd9ffb5
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-08-18 10:49:27 +01:00
Manish V Badarkhe cb55615c50 el3_runtime: Rearrange context offset of EL1 sys registers
SCTLR and TCR registers of EL1 plays role in enabling/disabling of
page table walk for lower ELs (EL0 and EL1).
Hence re-arranged EL1 context offsets to have SCTLR and TCR registers
values one after another in the stack so that these registers values
can be saved and restored using stp and ldp instruction respectively.

Change-Id: Iaa28fd9eba82a60932b6b6d85ec8857a9acd5f8b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-08-18 10:49:27 +01:00
Manish V Badarkhe e1c4933372 lib/cpus: Report AT speculative erratum workaround
Reported the status (applies, missing) of AT speculative workaround
which is applicable for below CPUs.

 +---------+--------------+
 | Errata  |      CPU     |
 +=========+==============+
 | 1165522 |  Cortex-A76  |
 +---------+--------------+
 | 1319367 |  Cortex-A72  |
 +---------+--------------+
 | 1319537 |  Cortex-A57  |
 +---------+--------------+
 | 1530923 |  Cortex-A55  |
 +---------+--------------+
 | 1530924 |  Cortex-A53  |
 +---------+--------------+

Also, changes are done to enable common macro 'ERRATA_SPECULATIVE_AT'
if AT speculative errata workaround is enabled for any of the above
CPUs using 'ERRATA_*' CPU specific build macro.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I3e6a5316a2564071f3920c3ce9ae9a29adbe435b
2020-08-18 10:49:27 +01:00