Commit Graph

4346 Commits

Author SHA1 Message Date
Madhukar Pappireddy 866e6721f3 Merge changes from topic "scmi_v2_0" into integration
* changes:
  drivers/arm/css/scmi: Update power domain protocol version to 2.0
  tc0: update GICR base address
2021-04-15 23:39:31 +02:00
Usama Arif 69f2ace106 tc0: update GICR base address
The number of ITS have changed from 4 to 1, resulting
in GICR base address change.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7
2021-04-14 12:13:26 +01:00
Madhukar Pappireddy 511c7f3a9d Merge changes from topic "dcc_console" into integration
* changes:
  plat:xilinx:versal: Add JTAG DCC support
  plat:xilinx:zynqmp: Add JTAG DCC support
  drivers: dcc: Support JTAG DCC console
2021-04-13 21:42:55 +02:00
Olivier Deprez 3b9e06a6dd Merge "plat/arm: don't provide NT_FW_CONFIG when booting hafnium" into integration 2021-04-13 14:16:08 +02:00
Madhukar Pappireddy 29e11bb299 Merge "driver: brcm: add USB driver" into integration 2021-04-12 16:44:11 +02:00
Madhukar Pappireddy bab737d397 Merge "driver: brcm: add mdio driver" into integration 2021-04-12 16:43:48 +02:00
Manish Pandey 2b6fc53584 plat/arm: don't provide NT_FW_CONFIG when booting hafnium
NT_FW_CONFIG file is meant to be passed from BL31 to be consumed by
BL33, fvp platforms use this to pass measured boot configuration and
the x0 register is used to pass the base address of it.

In case of hafnium used as hypervisor in normal world, hypervisor
manifest is expected to be passed from BL31 and its base address is
passed in x0 register.

As only one of NT_FW_CONFIG or hypervisor manifest base address can be
passed in x0 register and also measured boot is not required for SPM so
disable passing NT_FW_CONFIG.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ifad9d3658f55ba7d70f468a88997d5272339e53e
2021-04-09 16:40:47 +01:00
Yann Gautier cddf1bd765 plat/st: do not keep mmc_device_info in stack
Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].

 [1] 13f3c5166f ("mmc:prevent accessing to the released space in case of wrong usage")

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I73a079715253699d903721c865d6470d58f6bd30
2021-04-08 08:44:57 +02:00
Yann Gautier 5cb7fc8263 plat/intel: do not keep mmc_device_info in stack
Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].

 [1] 13f3c5166f ("mmc:prevent accessing to the released space in case of wrong usage")

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Id52c0be61a30f453a551385883eaf3cbe32b04b9
2021-04-08 08:44:57 +02:00
Yann Gautier 9171ced341 plat/hisilicon: do not keep mmc_device_info in stack
Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].

 [1] 13f3c5166f ("mmc:prevent accessing to the released space in case of wrong usage")

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: If5db8857cccec2e677b16a38eb3eeb41628a264c
2021-04-08 08:44:57 +02:00
Madhukar Pappireddy 51672950ee Merge changes from topic "my-topic-name" into integration
* changes:
  plat: imx8mm: Add image load logic for TBBR FIP booting
  plat: imx8mm: Add initial defintions to facilitate FIP layout
  plat: imx8mm: Add image io-storage logic for TBBR FIP booting
  plat: imx8mm: Add imx8mm_private.h to the build
2021-04-07 17:59:43 +02:00
Heyi Guo abe6ce1d1b plat/arm/arm_image_load: refine plat_add_sp_images_load_info
Refine the function plat_add_sp_images_load_info() by saving the
previous node and only setting its next link when the current node is
valid. This can reduce the check for the next node and simply the
total logic.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I4061428bf49ef0c3816ac22aaeb2e50315531f88
2021-04-06 17:17:33 +01:00
Heyi Guo 47fe4c4fe2 plat/arm/arm_image_load: fix bug of overriding the last node
The traverse flow in function plat_add_sp_images_load_info() will find
the last node in the main load info list, with its
next_load_info==NULL. However this node is still useful and should not
be overridden with SP node info.

The bug will cause below error on RDN2 for spmd enabled:

ERROR:   Invalid NT_FW_CONFIG DTB passed

Fix the bug by only setting the next_load_info of the last node in the
original main node list.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Icaee5da1f2d53b29fdd6085a8cc507446186fd57
2021-04-06 17:16:43 +01:00
Venkatesh Yadav Abbarapu 0b25f4045a plat:xilinx:versal: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I77994ce387caf0d695986df3d01d414a920978d0
2021-03-31 22:00:21 -06:00
Venkatesh Yadav Abbarapu c00baeecbb plat:xilinx:zynqmp: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I62cfbb57ae7e454fbc91d1c54aafa6e99f9a35c8
2021-03-31 22:00:04 -06:00
Bipin Ravi 0a144dd4ea Add Cortex_A78C CPU lib
Add basic support for Cortex_A78C CPU.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56
2021-03-31 16:02:35 -05:00
André Przywara 8078b5c5a0 Merge changes from topic "allwinner_h616" into integration
* changes:
  allwinner: H616: Add reserved-memory node to DT
  allwinner: Add Allwinner H616 SoC support
  allwinner: Add H616 SoC ID
  allwinner: Express memmap more dynamically
  allwinner: Move sunxi_cpu_power_off_self() into platforms
  allwinner: Move SEPARATE_NOBITS_REGION to platforms
  doc: allwinner: Reorder sections, document memory mapping
2021-03-30 16:21:13 +02:00
bipin.ravi e5fa7459ed Merge "Add Makalu ELP CPU lib" into integration 2021-03-29 22:41:29 +02:00
Madhukar Pappireddy cba9c0c2aa Merge changes from topic "rd_updates" into integration
* changes:
  plat/sgi: allow usage of secure partions on rdn2 platform
  board/rdv1mc: initialize tzc400 controllers
  plat/sgi: allow access to TZC controller on all chips
  plat/sgi: define memory regions for multi-chip platforms
  plat/sgi: allow access to nor2 flash and system registers from s-el0
  plat/sgi: define default list of memory regions for dmc620 tzc
  plat/sgi: improve macros defining cper buffer memory region
  plat/sgi: refactor DMC-620 error handling SMC function id
  plat/sgi: refactor SDEI specific macros
2021-03-29 20:42:49 +02:00
Omkar Anand Kulkarni c0d55ef7c0 plat/sgi: allow usage of secure partions on rdn2 platform
Add the secure partition mmap table and the secure partition boot
information to support secure partitions on RD-N2 platform. In addition
to this, add the required memory region mapping for accessing the
SoC peripherals from the secure partition.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I2c75760d6c8c3da3ff4885599be420e924aeaf3c
2021-03-29 22:00:30 +05:30
Sandrine Bailleux 27d593ad95 Merge changes from topic "tzc400_stm32mp" into integration
* changes:
  stm32mp1: add TZC400 interrupt management
  stm32mp1: use TZC400 macro to describe filters
  tzc400: add support for interrupts
2021-03-29 18:20:58 +02:00
Aditya Angadi f97b579502 board/rdv1mc: initialize tzc400 controllers
A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM memory. Configure each of the TZC controllers
across the Chips.

For use by secure software, configure the first chip's trustzone
controller to protect the upper 16MB of the memory of the first DRAM
block for secure accesses only. The other regions are configured for
non-secure read write access. For all the remote chips, all the DRAM
regions are allowed for non-secure read and write access.

Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I809f27eccadfc23ea0ef64e2fd87f95eb8f195c1
2021-03-29 21:36:48 +05:30
Aditya Angadi 2180349117 plat/sgi: allow access to TZC controller on all chips
On a multi-chip platform, the boot CPU on the first chip programs the
TZC controllers on all the remote chips. Define a memory region map for
the TZC controllers for all the remote chips and include it in the BL2
memory map table.

In addition to this, for SPM_MM enabled multi-chip platforms, increase
the number of mmap entries and xlat table counts for EL3 execution
context as well because the shared RAM regions and GIC address space of
remote chips are accessed.

Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I6f0b5fd22f9f28046451e382eef7f1f9258d88f7
2021-03-29 21:34:20 +05:30
Aditya Angadi 05b5c4175b plat/sgi: define memory regions for multi-chip platforms
For multi-chip platforms, add a macro to define the memory regions on
chip numbers >1 and its associated access permissions. These memory
regions are marked with non-secure access.

Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: If3d6180fd8ea61f45147c39d3140d694abf06617
2021-03-29 18:52:34 +05:30
Thomas Abraham 5dae6bc71c plat/sgi: allow access to nor2 flash and system registers from s-el0
Allow the access of system registers and nor2 flash memory region
from s-el0. This allows the secure parititions residing at s-el0
to access these memory regions.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I3887a86770de806323fbde0d20fdc96eec6e0c3c
2021-03-29 18:52:34 +05:30
Thomas Abraham b4d548f141 plat/sgi: define default list of memory regions for dmc620 tzc
Define a default DMC-620 TZC memory region configuration and use it to
specify the TZC memory regions on sgi575, rdn1edge and rde1edge
platforms. The default DMC-620 TZC memory regions are defined
considering the support for secure paritition as well.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: Iedee3e57d0d3de5b65321444da51ec990d3702db
2021-03-29 18:52:34 +05:30
Thomas Abraham d306eb801e plat/sgi: improve macros defining cper buffer memory region
Remove the 'ARM_' prefix from the macros defining the CPER buffer memory
and replace it with 'CSS_SGI_' prefix. These macros are applicable only
for platforms supported within plat/sgi. In addition to this, ensure
that these macros are defined only if the RAS_EXTENSION build option is
enabled.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I44df42cded18d9d3a4cb13e5c990e9ab3194daee
2021-03-29 18:52:34 +05:30
Thomas Abraham 513ba5c973 plat/sgi: refactor DMC-620 error handling SMC function id
The macros defining the SMC function ids for DMC-620 error handling are
listed in the sgi_base_platform_def.h header file. But these macros are
not applicable for all platforms supported under plat/sgi. So move these
macro definitions to sgi_ras.c file in which these are consumed. While
at it, remove the AArch32 and error injection function ids as these are
unused.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I249b54bf4c1b1694188a1e3b297345b942f16bc9
2021-03-29 18:52:34 +05:30
Thomas Abraham a883447403 plat/sgi: refactor SDEI specific macros
The macros specific to SDEI defined in the sgi_base_platform_def.h are
not applicable for all the platforms supported by plat/sgi. So refactor
the SDEI specific macros into a new header file and include this file on
only on platforms it is applicable on.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I0cb7125334f02a21cae1837cdfd765c16ab50bf5
2021-03-29 18:52:34 +05:30
Bharat Gooty 48c6a6b650 driver: brcm: add i2c driver
Broadcom I2C controller driver. Follwoing API's are supported:-
- i2c_init() Intialize ethe I2C controller
- i2c_probe()
- i2c_set_bus_speed() Set the I2C bus speed
- i2c_get_bus_speed() Get the current bus speed
- i2c_recv_byte() Receive one byte of data.
- i2c_send_byte() Send one byteof data
- i2c_read_byte() Read single byte of data
- i2c_read() Read multiple bytes of data
- i2c_write_byte Write single byte of data
- i2c_write() Write multiple bytes of data

This driver is verified by reading the DDR SPD data.

Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Change-Id: I2d7fe53950e8b12fab19d0293020523ff8b74e13
2021-03-26 16:22:55 +01:00
Andre Przywara 0be10ee373 allwinner: H616: Add reserved-memory node to DT
When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure
we tell the non-secure world about the memory region it uses.

Add a reserved-memory node to the DT, which covers the area that BL31
could occupy. The "no-map" property will prevent OSes from mapping
the area, so there would be no speculative accesses.

Change-Id: I808f3e1a8089da53bbe4fc6435a808e9159831e1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-26 10:19:27 +00:00
Andre Przywara 26123ca353 allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.

The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.

Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-25 15:25:54 +00:00
Andre Przywara bb104f27d4 allwinner: Add H616 SoC ID
Change-Id: I557fd05401e24204952135cf3ca26479a43ad1f1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-25 15:25:54 +00:00
Andre Przywara 01cec8f40c allwinner: Express memmap more dynamically
In preparation for changing the memory map, express the locations of the
various code and data pieces more dynamically, allowing SoCs to override
the memmap later.
Also prepare for the SCP region to become optional.

No functional change.

Change-Id: I7ac01e309be2f23bde2ac2050d8d5b5e3d6efea2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-25 15:25:54 +00:00
Andre Przywara 9227719dbf allwinner: Move sunxi_cpu_power_off_self() into platforms
The code to power the current core off when SCPI is not available is now
different for the two supported SoC families.
To make adding new platforms easier, move sunxi_cpu_power_off_self()
into the SoC directory, so we don't need to carry definitions for both
methods for all SoCs.

On the H6 we just need to trigger the CPUIDLE hardware, so can get rid
of all the code to program the ARISC, which is now only needed for the
A64 version.

Change-Id: Id2a1ac7dcb375e2fd021b441575ce86b4d7edf2c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-25 15:25:54 +00:00
Andre Przywara eb15bdaad2 allwinner: Move SEPARATE_NOBITS_REGION to platforms
For the existing SoCs we support, we use SEPARATE_NOBITS_REGION, to move
some parts of the data into separate memory regions (to save on the SRAM
A2 we are loaded into).
For the upcoming H616 platform this is of no concern (we run in DRAM),
so make this flag a platform choice instead.

Change-Id: Ic01d49578c6274660f8f112bd23680d3eca3be7a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-25 15:25:54 +00:00
André Przywara 9ad1031408 Merge "allwinner: Use CPUIDLE hardware when available" into integration 2021-03-25 13:29:50 +01:00
Andre Przywara 8fa5592b84 allwinner: A64: Limit FDT checks to reduce code size
The upcoming refactoring to support the new H616 SoCs will push the A64
build over the edge, by using more than the 48KB of SRAM available.

To reduce the code size, set some libfdt options that aim to reduce
sanity checks (for saving code space):
- ASSUME_LATEST: only allow v17 DTBs (as created by dtc)
- ASSUME_NO_ROLLBACK: don't prepare for failed DT additions
- ASSUME_LIBFDT_ORDER: assume sane ordering, as done by dtc

Change-Id: I12c93ec09e7587c5ae71e54947f817c32ce5fd6d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-25 13:28:35 +01:00
johpow01 cb090c1924 Add Makalu ELP CPU lib
Add basic support for Makalu ELP processor core.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7b1ddbb8dd43326ecb8ff188f6f8fcf239826a93
2021-03-24 12:53:18 -05:00
Joanna Farley 9719e19a97 Merge changes I500ddbe9,I9c10dac9,I53bfff85,I06f7594d,I24bff8d4, ... into integration
* changes:
  nxp lx2160a-aqds: new plat based on soc lx2160a
  NXP lx2160a-rdb: new plat based on SoC lx2160a
  nxp lx2162aqds: new plat based on soc lx2160a
  nxp: errata handling at soc level for lx2160a
  nxp: make file for loading additional ddr image
  nxp: adding support of soc lx2160a
  nxp: deflt hdr files for soc & their platforms
  nxp: platform files for bl2 and bl31 setup
  nxp: warm reset support to retain ddr content
  nxp: nv storage api on platforms
  nxp: supports two mode of trusted board boot
  nxp: fip-handler for additional fip_fuse.bin
  nxp: fip-handler for additional ddr-fip.bin
  nxp: image loader for loading fip image
  nxp: svp & sip smc handling
  nxp: psci platform functions used by lib/psci
  nxp: helper function used by plat & common code
  nxp: add data handler used by bl31
  nxp: adding the driver.mk file
  nxp-tool: for creating pbl file from bl2
  nxp: adding the smmu driver
  nxp: cot using nxp internal and mbedtls
  nxp:driver for crypto h/w accelerator caam
  nxp:add driver support for sd and emmc
  nxp:add qspi driver
  nxp: add flexspi driver support
  nxp: adding gic apis for nxp soc
  nxp: gpio driver support
  nxp: added csu driver
  nxp: driver pmu for nxp soc
  nxp: ddr driver enablement for nxp layerscape soc
  nxp: i2c driver support.
  NXP: Driver for NXP Security Monitor
  NXP: SFP driver support for NXP SoC
  NXP: Interconnect API based on ARM CCN-CCI driver
  NXP: TZC API to configure ddr region
  NXP: Timer API added to enable ARM generic timer
  nxp: add dcfg driver
  nxp:add console driver for nxp platform
  tools: add mechanism to allow platform specific image UUID
  tbbr-cot: conditional definition for the macro
  tbbr-cot: fix the issue of compiling time define
  cert_create: updated tool for platform defined certs, keys & extensions
  tbbr-tools: enable override TRUSTED_KEY_CERT
2021-03-24 17:31:38 +01:00
Pankaj Gupta f359a38224 nxp lx2160a-aqds: new plat based on soc lx2160a
New NXP platform lx2160a-qds:
- Based SoC lx2160a
- Board specific tuning for DDR init.
- Board specific Flash details.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I500ddbe9e56c4af5f955da6ecbd4ddc5fbe89a12
2021-03-24 09:49:32 +05:30
Pankaj Gupta eb2b193d75 NXP lx2160a-rdb: new plat based on SoC lx2160a
New NXP platform lx2160a-rdb(Reference Design Board):
- Based SoC lx2160a
- Board specific tuning for DDR init.
- Board specific Flash details.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I9c10dac9d5e67d44a2d94a7a27812220fdcc6ae3
2021-03-24 09:49:32 +05:30
Pankaj Gupta 1f49730869 nxp lx2162aqds: new plat based on soc lx2160a
New NXP platform lx2162aqds:
- Based SoC lx2160a
- Board specific tuning for DDR init.
- Board specific Flash details.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I53bfff85398313082db77c77625cb2d40cd9b1b1
2021-03-24 09:49:32 +05:30
Pankaj Gupta 9877084b2c nxp: errata handling at soc level for lx2160a
SoC erratas are handled as part of this commit.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I06f7594d19cc7fc89fe036a8a255300458cb36dd
2021-03-24 09:49:32 +05:30
Pankaj Gupta 18498657f0 nxp: make file for loading additional ddr image
- NXP SoC lx2160a needs additional ddr_fip.bin.

- There are three types of ddr image that can be created:
  -- ddr_fip.mk for creating fip_ddr.bin image for normal boot.
  -- ddr_fip_sb.mk for creating fip_ddr_sec.bin image for NXP CSF based
     CoT/secure boot.
  -- ddr_fip_tbbr.mk for creating fip_ddr_sec.bin image for MBEDTLS
     CoT/secure boot.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I24bff8d489f72da99f64cb79b2114faa9423ce8c
2021-03-24 09:49:32 +05:30
Pankaj Gupta 87056d3193 nxp: adding support of soc lx2160a
* NXP SoC is 16 A-72 core SoC.
* SoC specific defines are defined in:
  - soc.def
  - soc.h
* Called for BL2 and BL31 setup, SoC specific setup are implemented in:
  - soc.c
* platform specific helper functions implemented at:
  - aarch64/lx2160a_helpers.S
* platform specific functions used by 'plat/nxp/commpon/psci',
  etc. are implemented at:
  - aarch64/lx2160a.S
* platform specific implementation for handling PSCI_SYSTEM_RESET2:
  - aarch64/lx2160a_warm_rst.S

Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ib40086f9d9079ed9b22967baff518c6df9f408b8
2021-03-24 09:49:32 +05:30
Pankaj Gupta dc05e50b8d nxp: deflt hdr files for soc & their platforms
- Default header files for:
  -- plat/nxp/soc-lxxxx/include/soc.h uses:
	--- soc_default_base_addr.h
        --- soc_default_base_macros.h

  -- plat/nxp/soc-lxxxx/<$PLAT>/platform_def.h uses:
	--- plat_default_def.h: Every macro define can be overidden.

  -- include/common/tbbr/tbbr_img_def.h uses:
	--- plat_tbbr_img_def.h: platform specific new FIP image macros.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ic50003e27e87891be3cd18bdb4e14a1c7272d492
2021-03-24 09:49:32 +05:30
Pankaj Gupta b53c2c5f2d nxp: platform files for bl2 and bl31 setup
For NXP platforms:
- Setup files for BL2 and BL31
- Other supporting files.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I36a1183a0652701bdede9e02d41eb976accbb017
2021-03-24 09:49:32 +05:30
Pankaj Gupta 0f33f50e21 nxp: warm reset support to retain ddr content
NXP: Added warm reset handler to handle SMC PSCI_SYSTEM_RESET2
raised from kernel (> 5.4).

As part of first cold boot, DDR training data is stored in NV storage.

As part of this SMC handling, following things are done:
- DDR is put in self-refresh mode to retain the content of DDR.
- Reset cause is saved.
- Reset is triggered.

On next boot to last warm-reset, DDR training is restored from
the NV storage.

Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I8e4fb0824887af49e959c93825e2ab0ba887fc9d
2021-03-24 09:49:32 +05:30
Pankaj Gupta 7c2d17792d nxp: nv storage api on platforms
NV storage API(s) for NXP platforms, supported on:
- flexspi-nor
- SecMon - General Purpose Registers at Low-Power section,
           retains their content if backed by coined battery.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Id65dee4f28e7d6d2024407030039de33ebe0fa05
2021-03-24 09:49:32 +05:30