Commit Graph

39 Commits

Author SHA1 Message Date
Abdul Halim, Muhammad Hadi Asyrafi d191eb247a intel: common: Remove urgent from mailbox async
Remove urgent argument from asynchrounous mailbox command as any urgent
command should always be synchronous

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iaa64335db24df3a562470d0d1c3d6a3a71493319
2020-10-24 11:00:42 +08:00
Abdul Halim, Muhammad Hadi Asyrafi f8e6a09c64 intel: common: Improve mailbox driver readability
Use pre-defined macros for return values and common mailbox arguments

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I5d549ee5358aebadf909f79fda55e83ee9844a0e
2020-10-24 11:00:42 +08:00
Abdul Halim, Muhammad Hadi Asyrafi 516f32219b intel: common: Clean up mailbox and sip header
Sort and rearrange definitions in both mailbox and sip header to
increase readability and maintainability.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I5544c2f17efdf3174757c55afd8cc1062fbae856
2020-10-24 11:00:42 +08:00
Chee Hong Ang 7f56f240d3 intel: clear 'PLAT_SEC_ENTRY' in early platform setup
Ensure 'PLAT_SEC_ENTRY' is cleared during early platform
setup. This is to prevent the slave CPU cores jump to the stale
entry point after warm reset when using U-Boot SPL as first
stage boot loader.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I3294ce2f74aa691d0cf311fa30f27f9d4fb8800a
2020-10-24 11:00:42 +08:00
Tien Hock Loh e734ecd61d plat: intel: Add FPGAINTF configuration to when configuring pinmux
FPGAINTF wasn't enabled when configuring pinmux. This fixes the issue.

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: I5a6aacd504901b8f7327b2f4854b8a77d0c37019
2020-06-08 22:03:41 +00:00
Tien Hock Loh aea772dd7a plat: intel: set DRVSEL and SMPLSEL for DWMMC
DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
2020-06-08 22:03:34 +00:00
Sandrine Bailleux 351d358fed Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration 2020-02-28 10:51:49 +00:00
Sandrine Bailleux 8f74c884a7 Merge "intel: Fix argument type for mailbox driver" into integration 2020-02-28 10:23:10 +00:00
Abdul Halim, Muhammad Hadi Asyrafi 960896eb89 intel: Update RSU driver return code
Modify RSU driver error code for backward-compatibility with
Linux RSU driver

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib9e38d4017efe35d3aceeee27dce451fbd429fb5
2020-02-27 20:25:58 +08:00
Abdul Halim, Muhammad Hadi Asyrafi ea9b962776 intel: Fix argument type for mailbox driver
This patch comes as fixes for 'intel: Fix Coverity Scan Defects' patch.
Revert changing argument type from uint32_t to uint64_t to fix
incompatible cast issue. Fix said bug by using intermediate uint32_t
array as a more appropriate solution.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I344cdabd432cf0a0389b225c934b35d12f4c631d
2020-02-25 16:41:47 +08:00
Tien Hock, Loh d603fd3033 intel: Enable EMAC PHY in Intel FPGA platform
This initializes the EMAC PHY in both Stratix 10 and Agilex,
without this, EMAC PHY wouldn't work correctly.

Change-Id: I7e6b9e88fd9ef472884fcf648e6001fcb7549ae6
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
2020-02-25 10:19:51 +08:00
Sandrine Bailleux eda880ff8e Merge "intel: Fix Coverity Scan Defects" into integration 2020-02-20 09:53:26 +00:00
Abdul Halim, Muhammad Hadi Asyrafi a62b47b87a intel: Fix Coverity Scan Defects
Fix mailbox driver incompatible cast bug and control flow issue that
was flagged by Coverity Scan.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3f34e98d24e40139d31cf7d5b9b973cd2d981065
2020-02-20 13:56:35 +08:00
Sandrine Bailleux 78fcbd65be Merge "intel: Change boot source selection" into integration 2020-02-12 15:54:02 +00:00
Hadi Asyrafi 0c5d62ad7f intel: Introduce SMC support for mailbox command
This update allows normal world to send mailbox commands through SMC

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I587bea06422da90e5907d586495cd9e3bde900f6
2020-02-05 16:26:15 +08:00
Hadi Asyrafi e1f97d9c52 intel: Extend SiP service to support mailbox's RSU
Introduce support for RSU that can be initiated through SMC calls.

Added features as below:
- RSU status
- RSU update
- RSU HPS notify
- RSU get sub-partition

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I78d5a07688e43da99f03d77dfd45ffb4a78f2e4c
2020-02-05 16:26:14 +08:00
Hadi Asyrafi 77fc46971e intel: Change boot source selection
Platform handoff structure no longer includes boot source selection.
Hence, those settings can now be configured through socfpga_plat_def.h.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: If7ec6a03bb25156a6670ebf8f77105c370b553f6
2020-02-03 14:31:52 +08:00
Madhukar Pappireddy ca661a0092 Enable -Wredundant-decls warning check
This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently, this patch also fixes the issues reported by this
flag. Consider the following two lines of code from two different source
files(bl_common.h and bl31_plat_setup.c):

IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE);

The IMPORT_SYM macro which actually imports a linker symbol as a C expression.
The macro defines the __RO_START__ as an extern variable twice, one for each
instance. __RO_START__ symbol is defined by the linker script to mark the start
of the Read-Only area of the memory map.

Essentially, the platform code redefines the linker symbol with a different
(relevant) name rather than using the standard symbol. A simple solution to
fix this issue in the platform code for redundant declarations warning is
to remove the second IMPORT_SYM and replace it with following assignment

static const unsigned long BL2_RO_BASE = BL_CODE_BASE;

Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-01-28 11:09:02 -06:00
Deepika Bhavnani dc2d366fac intel: Unify Platform specific defines for PSCI module
PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Id3d3efc7e7711d19f0223da823713b8390ad2f47
2020-01-24 13:15:11 +00:00
Hadi Asyrafi f2decc7690 intel: Add function to check fpga readiness
Create a function to check for fpga readiness, and move the checking out
of bridge enable function.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3f473ffeffa9ce181a48977560c8bda19c6123c0
2020-01-16 10:56:43 +08:00
Hadi Asyrafi 20335ca8d5 intel: System Manager refactoring
Refactored system manager driver to be shared across both intel platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d
2020-01-16 10:53:26 +08:00
Hadi Asyrafi 391eeeef7f intel: Refactor reset manager driver
Refactor reset manager into intel common platform directory as it can be
shared by both Stratix 10 and Agilex. Register address and field is now
referred through macros.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a
2020-01-16 10:53:23 +08:00
Tien Hock, Loh 389091a8d6 plat: intel: Fix UEFI decompression issue
UEFI decompression will fail if the payload size is too large and the load
address is too low. This patch moves the payload to a higher address to fix
the issue

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I36087fbd2237b62891c59dbe2d34336bddfaa396
2020-01-15 13:41:34 +00:00
Hadi Asyrafi 32cf34acac intel: Implement platform specific system reset 2
Add support for platform specific warm-reset through psci system reset 2.

- system_reset2 implementation that calls for l2 cache reset
- Check for magic number and request for warm reset in bl2
- Create a shared reset manager header file for Agilex and Stratix 10
- Clean up parameter info in plat_get_next_bl_params

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3fdd9a2711c80d9bd3dc05b81527781d840bd726
2019-12-30 10:17:04 +08:00
Manish Pandey aeb3d83ecc Merge changes from topic "mailbox-fixes" into integration
* changes:
  intel: Fix SMC SIP service
  intel: Introduce mailbox response length handling
  intel: Fix mailbox config return status
  intel: Mailbox driver logic fixes
  plat: intel: Fix FPGA manager on reconfiguration
  plat: intel: Fix mailbox send_cmd issue
  intel: Modify mailbox's get_config_status
2019-12-19 17:33:03 +00:00
Manish Pandey 98ee29c6c4 Merge "intel: Create SiP service header file" into integration 2019-12-18 17:38:08 +00:00
Hadi Asyrafi 96612fcac4 intel: Introduce mailbox response length handling
Mailbox driver now handles variable response length

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic96854fdaadaf48379c5de688392df974e1c99c3
2019-12-17 19:45:29 +08:00
Hadi Asyrafi b68ba6cc79 intel: Fix mailbox config return status
Modify mailbox config return code to improve debugging.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I0a223291f4c5296203b3295a679a5857a446c692
2019-12-17 19:45:28 +08:00
Tien Hock, Loh cefb37eb39 plat: intel: Fix FPGA manager on reconfiguration
Fixes the SiP Service driver that is responsible for FPGA
reconfiguration. Also change the base address of FPGA reconfiguration
to 0x400000.

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I2b84c12c85cd5fc235247131fec4916ed2fb56c8
2019-12-17 19:45:24 +08:00
Tien Hock, Loh 68dd5e15eb plat: intel: Fix mailbox send_cmd issue
There are a few issues in mailbox that needs to be fixed.
- Send doorbell after an indirect cmd
- Do not ring doorbell when polling mailbox response as it should've been
sent by send_cmd
- remove unneeded cmd_free_offset check
- Fix mailbox initialization
- Fix get_config_status returning a wrong status when the status is busy
- Add command length in mailbox command header

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: If613e2ca889a540a616c62d69ad0086a7cd46536
2019-12-17 19:44:06 +08:00
Hadi Asyrafi 23f31d39bf intel: stratix10: Modify BL31 parameter handling
Add-in support for handling BL31 parameter from non-BL2 image, ie. SPL

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I16118d791399f652b6d1093c10092935a3449c32
2019-12-17 12:54:34 +08:00
Hadi Asyrafi cf82aff098 intel: Modify BL31 address mapping
Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use
of On-Chip RAM for BL31 specific variables filling down from handoff
offset to reduce fragmentation

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib64f48bd14f71e5fca2d406f4ede3386f2881099
2019-12-17 12:54:34 +08:00
Hadi Asyrafi 2db1e7663d intel: stratix10: Enable uboot entrypoint support
This patch will provide an entrypoint for uboot's spl into BL31.
BL31 will also handle secondary cpu state during uboot's cold boot

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I661bdb782c2d793d5fc3c7f78dd7ff746e33b7a3
2019-12-17 12:54:29 +08:00
Hadi Asyrafi ec7d0055c9 intel: Modify mailbox's get_config_status
Move the get_config_status out of sip_svc driver.
Modify the function so that it can return either
CONFIG_STATUS or RECONFIG_STATUS

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I642d5900339e67f98be61380edc2b838e0dd47af
2019-12-17 10:17:48 +08:00
Hadi Asyrafi d25041bf1e intel: Create SiP service header file
Separate SiP related definition from mailbox header file

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I45ba540f29d9261007f7ec23469358747cf140b4
2019-12-17 10:17:47 +08:00
Hadi Asyrafi d09adcbaf2 intel: Refactor common platform code [3/5]
Pull out mailbox driver into common area as they can be shared between
intel's socfpga platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716
2019-11-28 12:47:58 +08:00
Hadi Asyrafi e9b5e360de intel: Refactor common platform code [2/5]
Share socfpga private definitions and storage driver between Agilex and
Stratix 10 platform.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5
2019-11-28 12:47:58 +08:00
Hadi Asyrafi 328718f254 intel: Refactor common platform code [1/5]
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.

Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
2019-11-28 12:47:57 +08:00
Hadi Asyrafi 3f7b1490dc intel: Platform common code refactor
Pull out common code from aarch64 and include

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
2019-08-07 12:19:11 +00:00