Commit Graph

4949 Commits

Author SHA1 Message Date
Manish Pandey f7a92518f6 Merge changes from topic "st_ddr_updates" into integration
* changes:
  refactor(st-ddr): move basic tests in a dedicated file
  refactor(st-ddr): reorganize generic and specific elements
  feat(stm32mp1): allow configuration of DDR AXI ports number
  refactor(st-ddr): update parameter array initialization
  feat(st-ddr): add read valid training support
  refactor(stm32mp1): remove the support of calibration result
  fix(st-ddr): correct DDR warnings
2022-01-07 17:24:54 +01:00
Manish Pandey 32de790f02 Merge "fix(st): manage UART clock and reset only in BL2" into integration 2022-01-07 17:09:53 +01:00
Manish Pandey cbbcf9b118 Merge changes Ifea8148e,I73559522 into integration
* changes:
  fix(morello): include errata workaround for 1868343
  fix(errata): workaround for Rainier erratum 1868343
2022-01-06 12:01:41 +01:00
Yann Gautier 9e52d45fdf fix(st): manage UART clock and reset only in BL2
As the UART is already initialized, no need to check for UART clock
or reset in next BL. An issue can appear if the next BL device tree
(e.g HW_CONFIG) doesn't use the same clocks or resets (like SCMI ones).

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I044ef2386abe2d3dba5a53c3685440d64ca50a4f
2022-01-05 18:54:59 +01:00
Manoj Kumar f94c84baa2 fix(morello): include errata workaround for 1868343
This patch includes the errata workaround for erratum
1868343 for the Morello platform.

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Change-Id: Ifea8148e10946db2276560f90bf2f32bf12b9dcc
2022-01-05 17:16:42 +00:00
Manish Pandey 5b0962833a Merge changes I19f713de,Ib5bda93d,Id5dafc04,Id20e65e2 into integration
* changes:
  feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.3
  feat(plat/rcar3): modify type for Internal function argument
  feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53
  fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53
2022-01-05 17:28:13 +01:00
Nicolas Le Bayon 63d2159846 refactor(st-ddr): move basic tests in a dedicated file
These basic tests are generic and should be used independently of the
driver, depending on the plaftorm characteristics.

Change-Id: I38161b659ef2a23fd30a56e1c9b1bd98461a2fe4
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
2022-01-05 11:47:46 +01:00
Nicolas Le Bayon 06e55dc842 refactor(st-ddr): reorganize generic and specific elements
stm32mp_ddrctl structure contains DDRCTRL registers definitions.
stm32mp_ddr_info contains general DDR information extracted from DT.
stm32mp_ddr_size moves to the generic side.
stm32mp1_ddr_priv contains platform private data.

stm32mp_ddr_dt_get_info() and stm32mp_ddr_dt_get_param() allow to
retrieve data from DT. They are located in new generic c/h files in
which stm32mp_ddr_param structure is declared. Platform makefile
is updated.

Adapt driver with this new classification.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I4187376c9fff1a30e7a94407d188391547107997
2022-01-05 11:09:59 +01:00
Yann Gautier 88f4fb8fa7 feat(stm32mp1): allow configuration of DDR AXI ports number
A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default.
It will allow choosing single or dual AXI ports for DDR.

Change-Id: I48826a66a6f4d18df87e081c0960af89ddda1b9d
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-01-05 11:09:59 +01:00
Madhukar Pappireddy 64fc535972 Merge "feat(plat/mediatek/mt8195): improve SPM wakeup log" into integration 2022-01-04 20:10:25 +01:00
Manish Pandey 9b75d94718 Merge changes from topic "st_fixes" into integration
* changes:
  fix(stm32mp1): do not reopen debug features
  refactor(stm32mp1): improve DGBMCU driver
  fix(stm32mp1): set reset pulse duration to 31ms
2022-01-04 18:46:59 +01:00
Jona Stubbe 9565962c37 refactor(plat/rockchip/rk3399/drivers/gpio): reduce code duplication
Refactor the GPIO code to use a small lookup table instead of redundant or
repetitive code.

Signed-off-by: Jona Stubbe <tf-a@jona-stubbe.de>
Change-Id: Icf60385095efc1f506e4215d497b60f90e16edfd
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2022-01-04 15:26:43 +01:00
Yann Gautier 21cfa4531a fix(stm32mp1): do not reopen debug features
On closed chips, it is not allowed to open debug. The BSEC debug
register can not be rewritten.
On open chips, the debug is already open, no need to rewrite this
register. This part of code is just removed.
An INFO message is displayed if debug is disabled.
The freeze of the watchdog during debug is also removed.
In case of debug, this must be managed by the software that enables
the debugger.

Change-Id: I19fbd3c487bb1018db30fd599cfa94fe5090899f
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2022-01-04 13:30:53 +01:00
Nicolas Le Bayon a24d5947af refactor(stm32mp1): improve DGBMCU driver
Add function headers to improve readability.
Add asserts when required.
Use RCC_BASE address.

Change-Id: Ia545293f00167b6276331a986ea7aa08c006e004
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2022-01-04 13:30:53 +01:00
Yann Gautier 9a73a56c35 fix(stm32mp1): set reset pulse duration to 31ms
According to ST Application note AN5256 [1], the minimum reset pulse
duration should be set to 31ms on boards powered with discrete
regulators.

[1] https://www.st.com/resource/en/application_note/dm00561921.pdf

Change-Id: Ib6ed029ee8a4b95f75a80948fdd2154b4ebe484f
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2022-01-04 13:30:53 +01:00
André Przywara e752fa4a4c Merge "feat(allwinner): allow to skip PMIC regulator setup" into integration 2022-01-01 02:16:14 +01:00
Rex-BC Chen bc714bafe7 fix(mt8186): remove unused files in drivers/mcdi
We don't use mbox drivers which are implemented in these files for
mcdi, so remove related files from mcdi folder.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Idea5ebe5b25f91066ebd653cdcdafe65ca292b0f
2021-12-30 17:21:33 +08:00
Andre Przywara 67412e4d7a feat(allwinner): allow to skip PMIC regulator setup
For somewhat historical reasons we are doing some initial PMIC regulator
setup in BL31, as U-Boot does not (yet) have a PMIC driver. This worked
fine so far, but there is at least one board (OrangePi 3) that gets upset,
because the Ethernet PHY needs some *coordinated* bringup of *two*
regulators.

To avoid custom hacks, let's introduce a build option to keep doing the
regulator setup in TF-A. Defining SUNXI_SETUP_REGULATORS to 0 will break
support for some devices on some boards in U-Boot (Ethernet and HDMI),
but will allow to bring up the OrangePi 3 in Linux correctly. We keep
the default at 1 to not change the behaviour for all other boards.

After U-Boot gained proper PMIC support at some point in the future, we
will probably change the default to 0, to get rid of the less optimal
PMIC code in TF-A.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie8e2583d0396f6eeaae8ffe6b6190f27db63e2a7
2021-12-27 15:32:22 +00:00
Madhukar Pappireddy 93b153b5bf Merge changes from topic "st_regulator" into integration
* changes:
  feat(st-sdmmc2): manage cards power cycle
  feat(stm32mp1): register fixed regulator
  feat(st-drivers): introduce fixed regulator driver
  refactor(st): update CPU and VDD voltage get
  refactor(stm32mp1-fdts): update regulator description
  refactor(st-pmic): use regulator framework for DDR init
  feat(st-pmic): register the PMIC to regulator framework
  refactor(st-pmic): split initialize_pmic()
  feat(stm32mp1): add regulator framework compilation
  feat(regulator): add a regulator framework
  feat(stpmic1): add new services
  feat(stpmic1): add USB OTG regulators
  refactor(st-pmic): improve driver usage
  refactor(stpmic1): set stpmic1_is_regulator_enabled() as boolean
  refactor(stm32mp1): re-order drivers init
2021-12-24 00:13:50 +01:00
Madhukar Pappireddy b3c4101541 Merge changes from topic "uart1_console" into integration
* changes:
  feat(versal): add UART1 as console
  feat(zynqmp): add uart1 as console
2021-12-22 19:18:15 +01:00
Madhukar Pappireddy 0ca4b4b79e Merge changes from topic "clock_framework" into integration
* changes:
  feat(st): use newly introduced clock framework
  feat(clk): add a minimal clock framework
2021-12-22 19:17:57 +01:00
Pascal Paillet 967a8e63c3 feat(stm32mp1): register fixed regulator
Register fixed regulator in BL2.

Change-Id: I24292f549b2cd24fb717fbb68eb95af7aa68e3b9
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-12-22 14:04:32 +01:00
Yann Gautier c39c658e75 refactor(st): update CPU and VDD voltage get
Use regulator framework to get CPU and VDD power supplies.

Change-Id: Ice745fb21ff10e71ef811e747165499c2e19253e
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-12-22 14:04:32 +01:00
Nicolas Le Bayon ae7792e058 refactor(st-pmic): split initialize_pmic()
print_pmic_info_and_debug() prints the PMIC version ID and displays
regulator information if debug is enabled.
It is under DEBUG flag and called after initialize_pmic() in BL2.

Change-Id: Ib81a625740b7ec6abb49cfca05e44c69efaa4718
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2021-12-22 14:04:32 +01:00
Yann Gautier bba9fdee58 feat(stm32mp1): add regulator framework compilation
Add required macro PLAT_NB_RDEVS in platform code, and update
platform.mk to compile regulator framework.

Change-Id: I9dc7a0a4c4f5a23d9bedda368d407612c9cd21cd
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-12-22 14:04:32 +01:00
Yann Gautier 0c16e7d2fb refactor(stm32mp1): re-order drivers init
SYSCFG can be initialized later, after console is up, to display the
warnings or messages it could issue.
PMIC should be initialized earlier, before SYSCFG init.

Change-Id: Icc3a1366083a1b1fde7f0e173645449b4c04c49b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-22 14:04:32 +01:00
Yann Gautier 33667d299b feat(st): use newly introduced clock framework
Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /
stm32mp_clk_get_rate() with clk_enable() / clk_disable() /
clk_get_rate().

Change-Id: I15d2ce57b9499211fa522a1b53eeee9cf584c111
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
2021-12-22 13:08:09 +01:00
Gabriel Fernandez 847c6bc8e6 feat(clk): add a minimal clock framework
This is mainly a clock interface with clk_ops callbacks.
Those callbacks are: enable, disable, get_rate, set_parent,
and is_enabled.
This framework is compiled for STM32MP1.

Change-Id: I5119a2aeaf103ceaae7a60d9e423caf0c148d794
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
2021-12-22 13:07:23 +01:00
Venkatesh Yadav Abbarapu 2c791499c2 feat(versal): add UART1 as console
Currently only UART0 is handled as console device, fix the
code to support UART1 as console also.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ifcd3c331cf6ce4afb0074357c92fc4addb9438b6
2021-12-22 03:56:42 -07:00
Venkatesh Yadav Abbarapu ea66e4af0b feat(zynqmp): add uart1 as console
Currently only UART0 is handled as console device, fix the
code to support UART1 as console also.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I08f69b65b78b967ceb7159f4a467aa5982b1f791
2021-12-22 03:56:16 -07:00
Rex-BC Chen 24dd5a7b71 feat(plat/mediatek/mt8186): add reboot function for PSCI
Add system_reset function in PSCI operations.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I41001484f6244bd6ae7dedcfb6ce71cd6c035a1e
2021-12-22 18:06:53 +08:00
Rex-BC Chen a68346a772 feat(plat/mdeiatek/mt8186): add power-off function for PSCI
Add support for system-off.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic734696aab1b71ae85bca6ed08e544a522ce5c95
2021-12-22 18:06:53 +08:00
Rex-BC Chen 572f8adbb0 feat(plat/mediatek/mt8186): apply erratas for MT8186
MT8186 uses Cortex A76 CPU, so we apply these erratas.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I84741535fbe429f664092f624c2da653532204cd
2021-12-22 18:06:53 +08:00
Garmin.Chang 06cb65ef07 feat(plat/mediatek/mt8186): add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.

TEST=build pass
BUG=b:202871018

Change-Id: I85aaaf3a0e992a39d17c58f3d9d5ff1b5770f748
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
2021-12-22 18:06:53 +08:00
Garmin.Chang 1da57e54b2 feat(plat/mediatek/mt8186): add CPU hotplug
Implement PSCI platform operations to support CPU hotplug and MCDI.

TEST=bringup 8 CPUs successfully on kernel stage.
BUG=b:202871018

Change-Id: Ibd5423b70b3ca3f91edaa48d7ca5bc094e751510
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
2021-12-22 18:06:53 +08:00
Yuchen Huang 6e5d76bac8 feat(plat/mediatek/mt8186): add RTC drivers
Add RTC drivers for EOSC calibration.

TEST=build pass
BUG=b:202871018

Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: Ib48c07204c4a614072ba710c042794b59e8a902a
2021-12-22 18:06:53 +08:00
Rex-BC Chen 0fe7ae9c64 fix(plat/mediatek/mt8186): extend MMU region size
In mt8186 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn't include in the MMU mapping region. It triggers MMU faults.

This patch extends the MMU region 0 size to cover all mt8186 HW modules.
This patch also remove MMU region 1 because region 0 covers region 1.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I520c51338578bd68756cd02603ce6783f93daf51
2021-12-22 18:06:53 +08:00
Edward-JW Yang 95ea87ffc2 feat(plat/mediatek/mt8186): add DCM driver
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.

1. Add MCUSYS related DCM drivers.
2. Enable MCUSYS related DCM by default.

TEST=build pass
BUG=b:202871018

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Idc669364c89cde0974d2940bd12987ee833d1965
2021-12-22 18:06:53 +08:00
Guodong Liu af5a0c40af feat(plat/mediatek/mt8186): add pinctrl support
Add MT8186 pinctrl support.

TEST=build pass
BUG=b:202871018

Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I5b9c1c60a91c74c7d3f45c78a9403544373fa90f
2021-12-22 18:06:53 +08:00
Zhengnan Chen 109b91e38c feat(plat/mediatek/mt8186): add sys_cirq support
Add 8186 sys_cirq info.

TEST=build pass
BUG=b:202871018

Signed-off-by: Zhengnan Chen <zhengnan.chen@mediatek.corp-partner.google.com>
Change-Id: Ib8a1c4e995288bf5f7981ea65f27727715fe5787
2021-12-22 18:06:53 +08:00
Christine Zhu 206f125cc1 feat(plat/mediatek/mt8186): initialize GIC
Initialize GIC for mt8186.

TEST=build pass
BUG=b:202871018

Signed-off-by: Christine Zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I8d029983c7ce48fa116fafa7fa78c65349308014
2021-12-22 18:06:53 +08:00
Rex-BC Chen 5aab27dc42 feat(plat/mediatek/mt8186): add SiP service
Add the basic SiP service.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4dcc7383237bb6c1f2494920cde21197754f6367
2021-12-22 18:06:53 +08:00
James Lo 5bc88ec61c feat(plat/mediatek/mt8186): add pwrap and pmic driver
1. Add 8186 pwrap driver to access pmic.
2. Add 6366 pmic driver to support clean PWRHOLD.

TEST=build pass
BUG=b:202871018

Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: I3bc90460a6a55dff8d3293e04482abcad789bbb2
2021-12-22 18:06:53 +08:00
Rex-BC Chen d73e15e66a feat(plat/mediatek/mt8186): initialize delay_timer
Initialize delay_timer for delay functions.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib8f52d1c674537795cc478015c83cca0f872df60
2021-12-22 18:06:53 +08:00
Rex-BC Chen a6a0af57c3 feat(plat/mediatek/mt8186): initialize systimer
Add systimer to support timer function.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I505f7d094410d178e4203e3a9294b851a30ba150
2021-12-22 18:06:53 +08:00
Penny Jan 1b17e34c5d feat(plat/mediatek/mt8186): add EMI MPU basic driver
EMI MPU stands for external memory interface memory protect unit.
MT8186 supports 32 regions and 16 domains.
We add basic driver currently, and will add more settings for
EMI MPU in next patch.

TEST=build pass
BUG=b:202871018

Signed-off-by: Penny Jan <penny.jan@mediatek.corp-partner.google.com>
Change-Id: Ia9e5030164e40e060a05e8f91d2ac88258c2e98e
2021-12-22 18:06:48 +08:00
Bipin Ravi c2d75fa7a3 Merge "fix(errata): workaround for Cortex X2 erratum 2083908" into integration 2021-12-22 01:10:54 +01:00
Madhukar Pappireddy f480c9c42b Merge "fix(stm32mp1): correct include order" into integration 2021-12-17 20:04:33 +01:00
Yann Gautier ff7675ebf9 fix(stm32mp1): correct include order
Warnings about header files include order were triggered by CI.
Correct the include order to mathc CI requirements.

Change-Id: Iaca959add924e0e1fa2e56fab2348f0ee36e5fa7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-17 09:53:04 +01:00
johpow01 1db6cd6027 fix(errata): workaround for Cortex X2 erratum 2083908
Cortex X2 erratum 2083908 is a Cat B erratum present in the Cortex
X2 core. It applies to revision r2p0 and is still open.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Id9dca2b042bf48e75fb3013ab37d1c5925824728
2021-12-16 23:22:27 +01:00