SoC UART1 is internally connected to MCP UART1 so this
cannot be used as AP runtime UART instead we use the
IOFPGA UART0 as the AP runtime UART.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: Iecefb0d2cb875b3ecf97e0983b06f6e914835021
This patch adds support to load nt_fw_config
with the information from plat_info sds
structure which is then passed from BL2 to BL33.
Signed-off-by: sah01 <sahil@arm.com>
Change-Id: I2242da7404c72a4f9c2e3d7f3b5c154890a78526
Different platform_info sds struct definition will be used
for fvp and soc.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I92f0e1b2d0d755ad0405ceebfeb78d6e4c67013d
This patch adds all SOC and FVP related changes required to boot
a standard TBBR style boot on Morello.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: Ib8f7f326790b13082cbe8db21a980e048e3db88c
Based on the SCC configuration value obtained from the SDS
platform information structure configure DMC-Bing Server or
Client mode after zeroing out the memory.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I0555fa06c9c1906264848f4e32ca413b4742cdee
For Morello SoC, we use ECC capability for the RDIMMs
which require the entire DDR memory space to be zeroed
out before it can be accessed.
Change-Id: Icbe9916f9a2d3c4ce839d8bf7f867efa18f33e23
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
The same folder "plat/arm/board/morello" is going to be
used by both Morello FVP and Morello SoC platforms.
TARGET_PLATFORM build flag has been introduced to
differentiate between the two platforms
Change-Id: I3e94da372a3f1ba810b4259b85dd4c204306c359
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
There might be several platforms which use the
TARGET_PLATFORM build option to differentiate the code
between the platform variants.
Use of TARGET_PLATFORM in the common code leads to build
failures instead use PLAT build option.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I9724caf875bd56225e035ecffa8b9ca1a50d3401
Protect the UART instance used for serial boot
with UART used for console.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ieee1557b34e7baa81594c3fbf0513191737027bf
Use stm32mp_uart_console_setup() in SP_min setup.
Adapt the function stm32mp_uart_console_setup() for BL32 (no reset, add
CONSOLE_FLAG_RUNTIME under DEBUG.
Change-Id: Ib2d35c8d285dafb680aa218872ad679cbf43d0ed
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Use newly created function stm32mp_uart_console_setup().
And remove now useless code.
Change-Id: Ib8d0319d3f4f54309848bc225b58608cea73bad9
Signed-off-by: Yann Gautier <yann.gautier@st.com>
To ease console configuration, a dedicated function is created:
stm32mp_uart_console_setup(). The code will also be common for the
different BLs.
Change-Id: Idf3cad756f125ca2313cf30b1311637a9df8f27f
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Add function stm32_get_boot_interface to get the current boot interface
from information saved in the TAMP register.
Change-Id: I23af43c68eeaebe4c45920a57d739117aea3fbb1
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
The function stm32_save_boot_interface()is moved to stm32mp1_private.c
file. The files stm32mp1_context.{c,h} are removed.
As return is always 0, change the function to return void.
Call it earlier, to be able to use it when configuring console.
Change-Id: I8986e1257dc8e8708eab044a51ea1f2426b16597
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Those pins are configured by ROM code, for serial boot use cases.
Their configs are reset if the boot is done on UART, but not on USB.
This should then be done in TF-A. This has to be done after clock
init, and before console is configured.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I29a9694e25fcf1665360dd71f73937f769c43b52
Add set_gpio_reset_cfg() to set a pin in its reset configuration:
analog, no-pull, speed low, and its secure configuration, thanks to
stm32_gpio_is_secure_at_reset().
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7b73c3636859f97fcc57f81cf68b42efc727922e
Sort the compilation flags in platform.mk when checking and defining
them for C files.
Change-Id: I5a08399c89ede4c0bd8697045706122732205db5
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Thanks to dyn_cfg_dtb_info_get_index(), we can check if TOS_FW_CONFIG
is inside the FIP partition. If not we can skip its treatment when
populating FIP images.
Change-Id: If5623eabd1ba484549d4a908d4a6f43325b36875
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Modify the type of the variable that stores the value for MPIDR
in the internal function from uint64_t to u_register_t.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ib5bda93d5432e0412132bddf41ead8ee3fcf9e46
Add new function so that the value of bit at WUPMSKCA57/53,
which points to CPU other than the BOOT CPU, is 1 at initialization.
Modify sequence so that value of each bit for CPU at WUPMSKCA57/53 is
basically 0 and target bit value is changed to 1 only when CPU_OFF.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id5dafc04e1dbaf265c8b67b903c335bb1af49914
With new gcc11.2 by default the -mbranch-protection is
set to "standard" which is leading to increase the text
section by 4Kb. As the ZynqMP uses the ARMv8 architecture,
so there is no impact when we disable the branch protection.
These instructions do not provide the branch protection in
architectures before Armv8.3-A.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I36f7a55abf99f50df2ee265255598d83b1f480c6
Implemented a platform function 'plat_mboot_measure_critical_data' to
measure critical data and record its measurement using the Event Log
driver.
'bl2_plat_mboot_finish' function invokes this platform function
immediately after populating the critical data.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ia198295c6e07ab26d436eab1ff90df2cf28303af
It doesn't look correct to use mbed TLS defines directly in the Event
Log driver as this driver may use another Crypto library in future.
Hence mbed TLS Crypto dependency on Event Log driver is removed by
introducing generic Crypto defines and uses those in the Event Log
driver to call Crypto functions.
Also, updated mbed TLS glue layer to map these generic Crypto defines
to mbed TLS library defines.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ibc9c751f60cbce4d3f3cf049b7c53b3d05cc6735
SynQuacer SoC contains a Cortex-M3 System Control Processor(SCP)
which manages system power.
This commit modifies the PSCI system_off handling to call SCMI,
same as other PSCI calls. System power-off is done by turing off
the ATX power supply through GPIO, this operation is transferred
to SCP.
Note that this commit modifies only the SCMI case, obsolete SCPI
implementation is not updated.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I6c1009e67cccd1eb5d14c338c3df9103d63709dd
The GTimer implemented on SynQuacer has similar issue found on Juno
wherein CNTBaseN.CNTFRQ can be written but does not reflect the value
of the CNTFRQ register in CNTCTLBase frame. This doesn't follow ARM ARM
in that the value updated in CNTCTLBase.CNTFRQ is not reflected
in CNTBaseN.CNTFRQ.
Hence enable the workaround (applied to Juno) for SynQuacer that updates
the CNTFRQ register in the Non Secure CNTBaseN frame.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I5204fb57f28c0945812814f008c4905ef0882e2b
Handle boot from UART with STM32CubeProgammer based on mmap io
for STM32MP15.
Depends-On: Iba84e8dfd67b9f30416efb0f6778e48ba1f75dad
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ibd719dd46a11da78633728675ef6639635b6cf67
Add a file to support the STMicroelectronics tool STM32CubeProgrammer
over UART in BL2 for STM32MP15x platform.
This tools is based on protocol defined in AN5275,
"USB DFU/USART protocols used in STM32MP1 Series bootloaders"
based on STM32 MCU protocols (AN3155, "USART protocol used
in the STM32 bootloader").
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I956c95d8de0a94d1eb8e61f043651dae7b838170
These registers make it is possible to do external resets of A3700
peripherals. Most peripherals are reset by clearing a particular bit,
but some need setting the bit. Reflect this via "_N" suffix in macro
names.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iacef5e671746b831b5beea9e4fdcc59d8de84edc
Commit 4333f95 ("fix(spm_mm): do not compile if SVE/SME is enabled")
introduced a comiple time check to verify if ENABLE_SVE_FOR_NS is set to
0 when SPM_MM build is enabled. To support SPM_MM builds on SGI/RD
platforms set ENABLE_SVE_FOR_NS to 0.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: If78ed7567f6d988795b2bc7f772a883783246964
MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an object
with wider essential type
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Ia0d13c3cfeb13d22b6fc7e8869cc713218302973
MISRA Violation: MISRA-C:2012 R.14.4
- The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essentially Boolean type.
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I8cf821a42015858200cc0c514600012c8f61061f
MISRA Violation: MISRA-C:2012 R.17.7
- The value returned by a function having non-void return type shall be
used ((void) missing for discarded return value.).
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I1e6a598b9fe6c571a3e5010ee832ef860dfe491d
MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I9c6dd8dba40db8067b46947ceff295732648612a
MISRA Violation: MISRA-C:2012 R.7.2
- A "u" or "U" suffix shall be applied to all integer constants that are
represented in an unsigned type
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iaf6db75e42913ddceccb803426287d0c47d7f31d
MISRA Violation: MISRA-C:2012 R.15.7
- All if . . else if constructs shall be terminated with an else statement
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iea32e32b5683f7accd7fac8d557957f05ed0f5c5
MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
a compound statement
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: If1ccaa2f254ac85a329295de501e2b5558e8ff43
MISRA Violation: MISRA-C:2012 R.10.1
- Operands shall not be of an inappropriate essential type.
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I67b5788054a136be8d764472c5d85528a5c4272f
MISRA Violation: MISRA-C:2012 R.20.7
- Expressions resulting from the expansion of macro parameters shall be
enclosed in parentheses
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Id913c556cab955c798809ad2bd08ca3e48e2231a
MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I73c056ff4df2f14e04c92a49ac5c97e578e82107
MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an object
with wider essential type.
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I67ac6b6b4b643f57e76a435345540e241c9a88b9
MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
a compound statement
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I82e924a77ee3afeb56fa18714e94cc4f6fff5a49
The clock and pll of mt8195 can be locked into security access
by device apc. Add clock and pll related SiP call for the access
from Kernel space.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I0c1f7d6c6abdd3b976492a0b776dc5b1d1f1512b
Adds support for SPMD with SPMC at S-EL1. A new config option SPMC_OPTEE
is added to support loading the special OP-TEE images when configured
with SPD=spmd. With or without SPMC_OPTEE. It should still be possible
to load another BL32 payload implementing a SPMC, provided that entry
point is the same as load address, that is, BL32_BASE.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: Ie61dcd1ee564688baee1b575030e63dc2bb85121
Renamed a macro 'INVALID_ID' to 'EVLOG_INVALID_ID' to avoid its clash
with other macro names and to show it is explicitly used for Event
Log driver.
Change-Id: Ie4c92b3cd1366d9a59cd6f43221e24734865f427
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
When the console verbosity is at maximum, fconf_populate_arm_sp()
prints the UUID and load address of each secure partition. However,
the load address has not been retrieved yet at this point, which means
all partitions show a zero load address.
Move the trace after we have retrieved the SP's load address from the
device tree to make it more meaningful.
Change-Id: I58ef7df6c9107a433f61113cafd8f0855c468d40
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
sha 4ce3e99a3 introduced printf format specifiers for fixed width
types, which uses PRI*64 instead of "ll" for 64 bit values.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ic6811cc1788c698adde0807e5f8ab5290a900a26
sha 4ce3e99a3 introduced printf format specifiers for fixed width
types, which uses PRI*64 instead of "ll" for 64 bit variables.
Change-Id: I09a8d174694d4b170a6ef2e4a03df13adc829c00
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Use long instead of long long on aarch64 for 64_t stdint types.
Introduce inttypes.h to properly support printf format specifiers for
fixed width types for such change.
Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
* changes:
feat(arm_fpga): write UART baud base clock frequency into DTB
feat(arm_fpga): query PL011 to learn system frequency
refactor(arm_fpga): move command line code into separate function
fix(fdt): avoid output on missing DT property
feat(arm_fpga): add ITS autodetection
feat(arm_fpga): determine GICR base by probing
feat(gicv3): introduce GIC component identification
feat(libfdt): also allow changing base address
fix(arm_fpga): avoid re-linking from executable ELF file
Correctly handle USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION request
in USB driver and support a different result than
USB_DESC_TYPE_CONFIGURATION with the new optional ops
get_other_speed_config_desc().
The support of this descriptor is optionnal and is only
required when high-speed capable device which can operate at its
other possible speed.
This patch allows to remove the pbuf update in usb_core_get_desc()
and solves an issue on USB re-enumeration on STM32MP15 platform
as the result of get_config_desc() is a const array.
This issue is not see on normal use-case, as the USB enumeration
is only done in ROM code and TF-A reuse the same USB descritors.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I8edcc1e45065ab4e45d48f4bc37b49120674fdb0
Since we now autodetect the actual system frequency, which is also used
as the base for the UART baudrate generation, we should update the value
currently hard-coded in the DT. Otherwise Linux will reprogram the
divider using a potentially wrong base rate, which breaks the UART
output.
Find the DT node referenced by the UART node as the clock rate, and set
the "clock-frequency" property in that node to the detected system
frequency. This will let Linux reprogram the divider to the same value,
preserving the actual baudrate.
Change-Id: Ib5a936849f2198577b86509f032751d5386ed2f8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The Arm FPGAs run in mostly one clock domain, which is used for the CPU
cores, the generic timer, and also the UART baudrate base clock. This
single clock can have different rates, to compensate for different IP
complexity. So far most images used 10 MHz, but different rates start to
appear.
To avoid patching both the arch timer frequency and UART baud base fixed
clock in the DTB manually, we would like to set the clock rate
automatically. Fortunately the SCP firmware has the actual clock rate
hard coded, and already programs the PL011 UART baud divider register
with the correct value to achieve a 38400 bps baudrate.
So read the two PL011 baudrate divider values and re-calculate the
original base clock from there, to use as the arch timer frequency. If
the arch timer DT node contains a clock-frequency property, we use that
instead, to support overriding and disabling this autodetection.
Change-Id: I9857fbb418deb4644aeb2816f1102796f9bfd3bb
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The code dealing with finding the command line and inserting that into
the DTB is somewhat large, and drowns the other DT handlers in our
fpga_prepare_dtb() function.
Move that code into a separate function, to improve readability.
Change-Id: I828203c4bb248d38a2562fcb6afdefedf3179f8d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Some FPGAs come with a GIC that has an ITS block configured. Since the
ITS sits between the distributor and redistributors, we can autodetect
that, and already adjust the GICR base address.
To also make this ITS usable, add an ITS node to our base DTB, and
remove that should we not find an ITS during the scan for the
redistributor. This allows to use the same TF-A binary for FPGA images
with or without an ITS.
Change-Id: I4c0417dec7bccdbad8cbca26fa2634950fc50a66
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
When an Arm Ltd GIC (Arm GIC-[567]00) is instantiated with one or more
ITSes, the ITS MMIO frames appear between the distributor and
redistributor addresses. This makes the beginning of the redistributor
region dependent on the existence and number of ITSes.
To support various FPGA images, with and without ITSes, probe the
addresses in question, to learn whether they accommodate an ITS or a
redistributor. This can be safely done by looking at the PIDR[01]
registers, which contain an ID code for each region, documented in the
Arm GIC TRMs.
We try to find all ITSes instantiated, and skip either two or four 64K
frames, depending on GICv4.1 support. At some point we will find the
first redistributor; this address we then update in the DTB.
Change-Id: Iefb88c2afa989e044fe0b36b7020b56538c60b07
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
For platforms where we don't know the number of cores at compile time,
the size of the GIC redistributor frame is then also undetermined, since
it depends on this number of cores.
On top of this the GICR base address can also change, when an unknown
number of ITS frames (including zero) take up space between the
distributor and redistributor.
So while those two adjustments are done for independent reasons, the
code for doing so is very similar, so we should utilise the existing
fdt_adjust_gic_redist() function.
Add an (optional) gicr_base parameters to the prototype, so callers can
choose to also adjust this base address later, if needed.
Change-Id: Id39c0ba83e7401fdff1944e86950bb7121f210e8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
When we build the convenience firmware package file for the Arm FPGA
boards (bl31.axf), we combine trampolines, the DTB and the actual BL31
code into one ELF file, which is more a "container with load addresses"
than an actual executable. So far ld was fine with us using bl31.elf as
an input file, but binutils 2.35 changed that and complains about
taking an *executable* ELF file as in *input* to the linker:
-----------------
aarch64-none-elf-ld.bfd: cannot use executable file 'build/arm_fpga/debug/./bl31/bl31.elf' as input to a link
-----------------
Fortunately we don't need the actual BL31 ELF file for *that* part of
the linking, so can use the just created bl31.bin binary version of it.
Actually that shrinks the file, as we needlessly included the .BSS
section in the final file before.
Using the binary works with both older and newer toolchains versions, so
let's do this unconditionally.
Change-Id: Ib7e697f8363499123f7cb860f118f182d0830768
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Replace double space with single space in stm32cubeprogrammer_usb.c.
Change-Id: I717b136119e85fe8e25dd540758525f995200458
Signed-off-by: Yann Gautier <yann.gautier@st.com>
* changes:
feat(plat/st/stm32mp1): add STM32MP_USB_PROGRAMMER target
feat(plat/st/stm32mp1): add USB DFU support for STM32MP1
feat(plat/st): add STM32CubeProgrammer support on USB
feat(drivers/st/usb): add device driver for STM32MP1
feat(plat/st): add a USB DFU stack
feat(drivers/usb): add a USB device stack
Add a support of USB as serial boot devices for STM32MP15x platform:
the FIP file is provide by STM32CubeProgrammer with the DFU protocol,
loaded in DDR at DWL_BUFFER_BASE address and then the io memmap is used.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I272c17c458ff1e9d0780f8fa22330c8a35533d19
Add the USB descriptor, the struct used for USB enumeration with
the function usb_dfu_plat_init().
The USB support is based on the usb lib and on the stm32mp1 usb driver.
The content of enumeration (the string descriptor) is identical to
ROM code to avoid the USB reset en re-enumeration needs.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I18b40649e8df83813a5a340b0eee44c9a3470e43
Add a file to support over USB the STMicroelectronics tool
STM32CubeProgrammer in BL2 for STM32MP15x platform.
This tools is based on DFU stack.
Change-Id: I48a8f772cb0e9b8be24c06847f724f0470c0f917
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add a stack to support the Universal Serial Bus Device Class
Specification for Device Firmware Upgrade (USB DFU v1.1).
This stack is based on the USB device stack (USBD).
Change-Id: I8a56411d184882b6a9e3617c6dfb859086b8f353
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This patch removes files that are not used by TF-R as well as
removes unused generic files from the TF-R makefile.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Idb15ac295dc77fd38735bf2844efdb73e6f7c89b
This change essentially reverts [1] by removing the BL31 workaround
forcing the dtb address when Hafnium is loaded as an Hypervisor.
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9569
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I302161d027261448113c66b7fafa9c11620b54ef
This change enables MPMM and adds, to the TC firmware configuration
device tree, the AMU counters representing the "gears" for the
Maximum Power Mitigation Mechanism feature of the Cortex-X2,
Cortex-A710 and Cortex-A510:
- Gear 0: throttle medium and high bandwidth vector and viruses.
- Gear 1: throttle high bandwidth vector and viruses.
- Gear 2: throttle power viruses only.
This ensures these counters are enabled and context-switched as
expected.
Change-Id: I6df6e0fe3a5362861aa967a78ab7c34fc4bb8fc3
Signed-off-by: Chris Kay <chris.kay@arm.com>
Including the FCONF Makefile today automatically places the FCONF
sources into the source list of the BL1 and BL2 images. This may be
undesirable if, for instance, FCONF is only required for BL31.
This change moves the BL1 and BL2 source appends out of the common
Makefile to where they are required.
BREAKING CHANGE: FCONF is no longer added to BL1 and BL2 automatically
when the FCONF Makefile (`fconf.mk`) is included. When including this
Makefile, consider whether you need to add `${FCONF_SOURCES}` and
`${FCONF_DYN_SOURCES}` to `BL1_SOURCES` and `BL2_SOURCES`.
Change-Id: Ic028eabb7437ae95a57c5bcb7821044d31755c77
Signed-off-by: Chris Kay <chris.kay@arm.com>
This has been introduced to simplify dependencies on the FDT wrappers.
We generally want to avoid pulling in components on a file-by-file
basis, particularly as we are trying to draw conceptual boxes around
components in preparation for transitioning the build system to CMake,
where dependencies are modelled on libraries rather than files.
Signed-off-by: Chris Kay <chris.kay@arm.com>
Change-Id: Idb7ee05a9b54a8caa3e07f36e608867e20b6dcd5
Chandni Cherukuri
sah01
Manoj Kumar
Madhukar Pappireddy
Yann Gautier
Yann Gautier
Edward-JW Yang
Takuya Sakata
Manish Pandey
Venkatesh Yadav Abbarapu
Manish V Badarkhe
Sandrine Bailleux
Masahisa Kojima
Tinghan Shen
Patrick Delaunay
Patrick Delaunay
Pali Rohár
Vijayenthiran Subramaniam
Rex-BC Chen
Abhyuday Godhasara
Flora Fu
Jens Wiklander
Scott Branden
André Przywara
Mark Dykes
Olivier Deprez
johpow01
Chris Kay