Commit Graph

894 Commits

Author SHA1 Message Date
Soby Mathew 8aa4e5f4eb docs: User-guide corrections for RESET_TO_BL31
This patch updates the user guide instructions for
RESET_TO_SP_MIN and RESET_TO_BL31 cases. The load
address for BL31 had to be updated because of increase
in code size. Also, information about PIE support when
RESET_TO_BL31=1 for FVP is added.

In the case of RESET_TO_SP_MIN, the RVBAR address
was wrong in the instruction. This is also corrected
in the patch.

Change-Id: I65fe6d28c5cf79bee0a11fbde320d49fcc1aacf5
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-12-17 15:25:49 +00:00
Antonio Niño Díaz 4dd62543b7
Merge pull request #1716 from miyatsu/marvell-doc-fix-20181210
docs: marvell: Fix typo in file build.txt
2018-12-17 11:54:16 +01:00
Soby Mathew 85456a9201
Merge pull request #1700 from jwerner-chromium/JW_crashfix
MULTI_CONSOLE_API fixes and cleanups
2018-12-10 14:00:01 +00:00
Ding Tao 5c31518cee docs: marvell: Fix typo in file build.txt
Replace "Uboot" with "Ubuntu".

Signed-off-by: Ding Tao <miyatsu@qq.com>
2018-12-10 09:31:23 +00:00
Julius Werner 63c52d0071 plat/common/crash_console_helpers.S: Fix MULTI_CONSOLE_API support
Crash reporting via the default consoles registered by MULTI_CONSOLE_API
has been broken since commit d35cc34 (Console: Use callee-saved
registers), which was introduced to allow console drivers written in C.
It's not really possible with the current crash reporting framework to
support console drivers in C, however we should make sure that the
existing assembly drivers that do support crash reporting continue to
work through the MULTI_CONSOLE_API.

This patch fixes the problem by creating custom console_putc() and
console_flush() implementations for the crash reporting case that do not
use the stack. Platforms that want to use this feature will have to link
plat/common/aarch64/crash_console_helpers.S explicitly.

Also update the documentation to better reflect the new reality (of this
being an option rather than the expected default for most platforms).

Change-Id: Id0c761e5e2fddaf25c277bc7b8ab603946ca73cb
Signed-off-by: Julius Werner <jwerner@chromium.org>
2018-12-06 16:10:32 -08:00
Antonio Niño Díaz 36bc633eec
Merge pull request #1653 from JackyBai/master
Add NXP i.MX8MQ basic support
2018-12-05 11:22:55 +01:00
Bai Ping 8113681992 plat: imx: Add i.MX8MQ basic support
i.MX8MQ is new SOC of NXP's i.MX8M family based on
A53. It can provide industry-leading audio, voice
and video processing for applications that scale
from consumer home audio to industrial building
automation and mobile computers

this patchset add the basic supoort to boot up
the 4 X A53. more feature will be added later.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-12-05 08:58:51 +08:00
Konstantin Porotchkin d03f7a3122 doc: marvell: Update build manual with new memory layouts
Add description for memory layouts used by EspressoBin v7 (DDR4)

Change-Id: I199d8b52580b26e560f14b503a6e99d32de4f284
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/61279
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-12-04 14:09:44 +02:00
Jeenu Viswambharan 63eb2410c1 docs: Add RAS framework documentation
Change-Id: Ibf2b21b12ebc0af5815fc6643532a3be9100bf02
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-11-26 14:51:41 +00:00
Jeenu Viswambharan e31d76fd16 docs: Add Exception Handling Framework documentation
Change-Id: I77d38758d18ba6dda1652b1b1e644fbfb14386cc
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-11-26 11:22:32 +00:00
Pete Batard 934bbea18b rpi3: fix bad formatting in rpi3.rst
d4fd0219 (pull request #1685) introduced unwanted formatting
such as bold/italic in the description for RPI3_USE_UEFI_MAP.
2018-11-20 16:28:16 +00:00
Pete Batard 4dcf1fade2 rpi3: add RPI3_USE_UEFI_MAP build option
The default Raspberry Pi 3 memory mapping for ATF is geared towards
the use of uboot + Linux. This creates issues when trying to use
ATF with an UEFI payload and Windows on ARM64.

We therefore introduce new build option RPI3_USE_UEFI_MAP, that
enables the build process to use an alternate memory mapping that
is compatible with UEFI + Windows (as well as UEFI + Linux).

Fixes ARM-software/tf-issues#649

Signed-off-by: Pete Batard <pete@akeo.ie>
2018-11-19 11:45:12 +00:00
Antonio Niño Díaz 0a650ee451
Merge pull request #1680 from pbatard/rpi3-runtime-uart
rpi3: add RPI3_RUNTIME_UART build option
2018-11-15 16:36:12 +01:00
Sughosh Ganu 8a3588a7c8 SPM: EHF: Build EHF module along with Secure Partition Manager
Add a dependency for building EL3 exception handling framework(EHF)
module with the secure partition manager(SPM).

The EHF module is needed for raising the core's running priority
before the core enters the secure partition, and lowering it
subsequently on exit from the secure partition.

Change-Id: Icbe2d0a63f00b46dc593ff3d86b676c9333506c3
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
2018-11-14 11:18:22 +05:30
Pete Batard 6d5c61de74 rpi3: add RPI3_RUNTIME_UART build option
Some OSes (e.g. Ubuntu 18.04 LTS on Raspberry Pi 3) may disable the
runtime UART in a manner that prevents the system from rebooting if
ATF tries to send runtime messages there.

Also, we don't want the firmware to share the UART with normal
world, as this can be a DoS attack vector into the secure world.

This patch fixes these 2 issues by introducing new build option
RPI3_RUNTIME_UART, that disables the runtime UART by default.

Fixes ARM-software/tf-issues#647

Signed-off-by: Pete Batard <pete@akeo.ie>
2018-11-13 13:53:37 +00:00
Antonio Niño Díaz e07666de14
Merge pull request #1605 from sivadur/integration
Add support new Xilinx Versal ACAP platform
2018-11-12 10:56:41 +01:00
Siva Durga Prasad Paladugu f91c3cb1df arm64: versal: Add support for new Xilinx Versal ACAPs
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with
leading-edge memory and interfacing technologies to deliver powerful
heterogeneous acceleration for any application. The Versal AI Core series has
five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm
Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time
processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines
optimized for high-precision floating point with low latency.

This patch adds Virtual QEMU platform support for
this SoC "versal_virt".

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-09 15:06:53 +05:30
Manish Pandey ed2c4f4a44 plat/arm: Support direct Linux kernel boot in AArch32
This option allows the Trusted Firmware to directly jump to Linux
kernel for aarch32 without the need of an intermediate loader such
as U-Boot.

Similar to AArch64 ARM_LINUX_KERNEL_AS_BL33 only available with
RESET_TO_SP_MIN=1 as well as BL33 and DTB are preloaded in memory.

Change-Id: I908bc1633696be1caad0ce2f099c34215c8e0633
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2018-11-05 17:11:03 +00:00
Antonio Niño Díaz eb47f14d73
Merge pull request #1623 from MISL-EBU-System-SW/a3700-support
Add support for Armada 3700 and COMPHY porting layer
2018-11-01 12:44:24 +01:00
Antonio Niño Díaz 392b1d591c
Merge pull request #1649 from Yann-lms/stm32mp1_doc_update
docs: stm32mp1: complete compilation and flashing steps
2018-10-30 15:47:48 +01:00
Soby Mathew cf0886e2f1
Merge pull request #1644 from soby-mathew/sm/pie_proto
Position Indepedent Executable (PIE) Support
2018-10-29 10:56:30 +00:00
Soby Mathew 3bd17c0fef Basic Makefile changes for PIE
Change-Id: I0b8ccba15024c55bb03927cdb50370913eb8010c
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-10-29 09:54:31 +00:00
Antonio Nino Diaz 37f647a4be docs: gxbb: Add documentation
Change-Id: Ie2465c1ccc482bd8eb5e5a71c580543095e4ba94
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-26 11:53:53 +01:00
Antonio Nino Diaz 6c9ada3150 Add sample crash console functions
Platforms that wish to use the sample functions have to add the file to
their Makefile. It is not included by default.

Change-Id: I713617bb58dc218967199248f68da86241d7ec40
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-25 09:56:09 +01:00
Antonio Nino Diaz 5341b42ec1 rpi3: Add mem reserve region to DTB if present
When a device tree blob is present at a known address, instead of, for
example, relying on the user modifying the Linux command line to warn
about the memory reserved for the Trusted Firmware, pass it on the DTB.

The current code deletes the memory reserved for the default bootstrap
of the Raspberry Pi and adds the region used by the Trusted Firmware.

This system replaces the previous one consisting on adding
``memmap=16M$256M`` to the Linux command line. It's also meant to be
used by U-Boot and any other bootloader that understands DTB files.

Change-Id: I13ee528475fb043d6e8d9e9f24228e37ac3ac436
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-24 13:54:41 +01:00
Antonio Niño Díaz 44445ae5d8
Merge pull request #1641 from jeenu-arm/ptrauth
AArch64: Enable lower ELs to use pointer authentication
2018-10-24 11:29:57 +02:00
Yann Gautier 1ebb915afe docs: stm32mp1: complete compilation and flashing steps
Add U-Boot compilation information.
Add a chapter about how to populate SD-card.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
2018-10-24 10:50:12 +02:00
Grzegorz Jaszczyk 42a293379e mvebu: cp110: introduce COMPHY porting layer
Some of COMPHY parameters depends on the hw connection between the SoC
and the PHY, which can vary on different boards e.g. due to different
wires length. Define the "porting layer" with some defaults
parameters. It ease updating static values which needs to be updated due
to board differences, which are now grouped in one place.

Example porting layer for a8k-db is under:
plat/marvell/a8k/a80x0/board/phy-porting-layer.h

If for some boards parameters are not defined (missing
phy-porting-layer.h), the default values are used
(drivers/marvell/comphy/phy-default-porting-layer.h)
and the following compilation warning is show:
"Using default comphy params - you may need to suit them to your board".

The common COMPHY driver code is extracted in order to be shared with
future COMPHY driver for A3700 SoC platforms

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-10-18 12:13:11 +03:00
Jorge Ramirez-Ortiz 7e532c4bf7 rcar-gen3: initial commit for the rcar-gen3 boards
Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
Date:   Thu Aug 30 21:26:41 2018 +0900
	Update IPL and Secure Monitor Rev1.0.22

General Information:
===================

This port has been tested on the Salvator-X Soc_id r8a7795 revision
ES1.1 (uses an SPD).

Build Tested:
-------------
ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls

$ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed

Other dependencies:
------------------
* mbed_tls:
  git@github.com:ARMmbed/mbedtls.git [devel]

  Merge: 68dbc94 f34a4c1
  Author: Simon Butcher <simon.butcher@arm.com>
  Date:   Thu Aug 30 00:57:28 2018 +0100

* optee_os:
  https://github.com/BayLibre/optee_os

  Until it gets merged into OP-TEE, the port requires Renesas' Trusted
  Environment with a modification to support power management.

  Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
  Date:   Thu Aug 30 16:49:49 2018 +0200
    plat-rcar: cpu-suspend: handle the power level
    Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>

* u-boot:
  The port has beent tested using mainline uboot.

  Author: Fabio Estevam <festevam@gmail.com>
  Date:   Tue Sep 4 10:23:12 2018 -0300

*linux:
  The port has beent tested using mainline kernel.

  Author: Linus Torvalds <torvalds@linux-foundation.org>
  Date:   Sun Sep 16 11:52:37 2018 -0700
      Linux 4.19-rc4

Overview
---------

BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered
at this exception level (the Renesas' ATF reference tree [1] resets into
EL1 before entering BL2 - see its bl2.ld.S)

BL2 initializes DDR (and i2c to talk to the PMIC on some platforms)
before determining the boot reason (cold or warm).

During suspend all CPUs are switched off and the DDR is put in
backup mode (some kind of self-refresh mode). This means that BL2 is
always entered in a cold boot scenario.

Once BL2 boots, it determines the boot reason, writes it to shared
memory (BOOT_KIND_BASE) together with the BL31 parameters
(PARAMS_BASE) and jumps to BL31.

To all effects, BL31 is as if it is being entered in reset mode since
it still needs to initialize the rest of the cores; this is the reason
behind using direct shared memory access to  BOOT_KIND_BASE and
PARAMS_BASE instead of using registers to get to those locations (see
el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
case).

Depending on the boot reason BL31 initializes the rest of the cores:
in case of suspend, it uses a MBOX memory region to recover the
program counters.

[1] https://github.com/renesas-rcar/arm-trusted-firmware
Tests
-----

* cpuidle
  -------
   enable kernel's cpuidle arm_idle driver and boot

* system suspend
  --------------
  $ cat suspend.sh
    #!/bin/bash
    i2cset -f -y 7 0x30 0x20 0x0F
    read -p "Switch off SW23 and press return " foo
    echo mem > /sys/power/state

* cpu hotplug:
  ------------
  $ cat offline.sh
    #!/bin/bash
    nbr=$1
    echo 0 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

  $ cat online.sh
    #!/bin/bash
    nbr=$1
    echo 1 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

Signed-off-by: ldts <jramirez@baylibre.com>
2018-10-17 18:38:33 +02:00
Jeenu Viswambharan 3ff4aaaca4 AArch64: Enable lower ELs to use pointer authentication
Pointer authentication is an Armv8.3 feature that introduces
instructions that can be used to authenticate and verify pointers.

Pointer authentication instructions are allowed to be accessed from all
ELs but only when EL3 explicitly allows for it; otherwise, their usage
will trap to EL3. Since EL3 doesn't have trap handling in place, this
patch unconditionally disables all related traps to EL3 to avoid
potential misconfiguration leading to an unhandled EL3 exception.

Fixes ARM-software/tf-issues#629

Change-Id: I9bd2efe0dc714196f503713b721ffbf05672c14d
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-10-16 08:31:13 +01:00
John Tsichritzis fadd21514b Fix typos in changelog
Change-Id: Icc6fb03abb9b4ef85931b9e3d767b5a9c271b5f3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-10-10 12:11:32 +01:00
John Tsichritzis ea75ffd3e7 docs: Clarify usage of LOG_LEVEL
Change-Id: I1ce771a155e6e83885a00d2f05591bf98cd69854
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-10-10 12:11:32 +01:00
Soby Mathew 3989a81930
Merge pull request #1609 from MISL-EBU-System-SW/integration-ble
plat/marvell: Move BLE into the platform tree, minor fix in tools.
2018-10-04 14:31:58 +01:00
Konstantin Porotchkin 37c4341b10 marvell: Move BLE from external repo to the platform folder
The BLE is the pre-TF-A boot stage required by Marvell Armada
BootROM for bringing up DRAM and allow the boot image copy to it.
Since this is not a standard boot level and only uses the TF-A
as a build environment, it was introduced out of source tree.
However it turns out that such remote location introduces additional
complexity to the upstream TF-A build process.
In order to simplify the build environment the BLE source folder
is relocated from the external repository to A8K platform directory.
The build documentation is updated accordingly.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-10-03 15:31:19 +03:00
Daniel Boulby 1dcc28cfba Introduce RECLAIM_INIT_CODE build flag
This patch introduces a build flag "RECLAIM_INIT_CODE" to mark boot time
code which allows platforms to place this memory in an appropriate
section to be reclaimed later. This features is primarily targeted for
BL31. Appropriate documentation updates are also done.

Change-Id: If0ca062851614805d769c332c771083d46599194
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-10-03 11:47:30 +01:00
Soby Mathew 034a8155f0
Merge pull request #1597 from antonio-nino-diaz-arm/an/optimise
plat/arm: Remove option ARM_BOARD_OPTIMISE_MEM
2018-10-03 11:18:30 +01:00
Soby Mathew fad365dfc8 docs: Fixup filename and links to compatibility policy
Change-Id: I9d14faa7294578443233b84d5459fa7b62a30c07
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-10-02 14:03:37 +01:00
Antonio Nino Diaz c0740e4fa6 plat/arm: Remove option ARM_BOARD_OPTIMISE_MEM
This option makes it hard to optimize the memory definitions of all Arm
platforms because any change in the common defines must work in all of
them. The best thing to do is to remove it and move the definition to
each platform's header.

FVP, SGI and SGM were using the definitions in board_arm_def.h. The
definitions have been copied to each platform's platform_def.h. Juno
was already using the ones in platform_def.h, so there have been no
changes.

Change-Id: I9aecd11bbc72a3d0d7aad1ef9934d8df21dcfaf2
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-02 14:00:32 +01:00
Soby Mathew 5eb48849c7
Merge pull request #1601 from joannafarley-arm/jf/release-2.0-changelog
Release docs updates for v2.0 release
2018-10-02 13:48:02 +01:00
Joanna Farley f9f26a5a31 Release docs updates for v2.0 release
Change-Id: Iaa5c586b65f0abdd4ddbdee4c73d07811a0aff49
Signed-off-by: Joanna Farley <joanna.farley@arm.com>
2018-10-02 12:12:02 +01:00
Soby Mathew ab2844b6da
Merge pull request #1600 from soby-mathew/sm/compat_policy_doc
docs: Add platform compatibility policy document
2018-10-02 11:21:46 +01:00
Soby Mathew 6e93eef40a docs: Add platform compatibility policy document
Information regarding platform compatibility policy
is added to the documentation.

Change-Id: If9f2a11160f81354ee2c678f0fca9d67fc7366e6
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-10-02 11:16:01 +01:00
Soby Mathew 848f00ce31
Merge pull request #1598 from soby-mathew/sm/docs_update_deprecate_1
docs: update for removal of deprecated interfaces.
2018-10-02 11:09:30 +01:00
Soby Mathew 509af92e0e docs: update for removal of deprecated interfaces.
Change-Id: I69e2720f534583a0f8d0e44f2e7b6f393f6fd093
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-10-01 16:19:24 +01:00
Antonio Nino Diaz 8cff97d1b4 zynqmp: Migrate to new interfaces
- Remove references to removed build options.
- Migrate to bl31_early_platform_setup2().

Change-Id: Ibeb8982a0a841f55ce778c4f09f06b72b47b21d8
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28 15:31:54 +01:00
Antonio Nino Diaz 90e0c98373 xlat: Remove deprecated interfaces
Change-Id: I83de2ae3e0795e6fec3c1e5b37c441b64b0c9cb6
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28 15:31:53 +01:00
Antonio Nino Diaz f9ed3cb624 gic: Remove deprecated driver and interfaces
Change-Id: I567a406edb090ae9d109382f6874846a79dd7473
Co-authored-by: Roberto Vargas <roberto.vargas@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28 15:31:53 +01:00
Antonio Nino Diaz e23e057e77 tbbr: Use USE_TBBR_DEFS=1 by default
Change-Id: I2885b0d8cb9bb16da1fa96a30e46cccde434dc42
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28 15:31:52 +01:00
Roberto Vargas ed51b51f7a Remove build option LOAD_IMAGE_V2
The code of LOAD_IMAGE_V2=0 has been removed.

Change-Id: Iea03e5bebb90c66889bdb23f85c07d0c9717fffe
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28 15:31:52 +01:00
Roberto Vargas 871de5373d PSCI: Remove platform compatibility layer
Change-Id: I40d040aa05bcbf11536a96ce59827711456b93a8
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28 15:31:52 +01:00
dp-arm dadb16eac2 fip_create: Remove fip_create compatibility script
A compatibility script has been provided for about 2 years. Users should
have migrated to fiptool by now so remove the compat script.

Change-Id: I643e0c40a9e3fb428bad3be04a82cb431aad74dc
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2018-09-28 15:31:52 +01:00
Soby Mathew 9068257ea7
Merge pull request #1585 from sandrine-bailleux-arm/sb/doc-fixes
Minor documentation fixes
2018-09-21 13:15:34 +01:00
Joanna Farley d83bf0bc10 Readme and Change-log updates for v1.6 release
Change-Id: I7855c9d3de104975bf3249bdf291c428f001d07a
Signed-off-by: Joanna Farley <joanna.farley@arm.com>
2018-09-21 09:23:52 +01:00
Sandrine Bailleux 1843a19974 User guide: Document ENABLE_SPM build flag
Change-Id: Ib9a045200de4fcd00387b114cbbd006e46ad6a8b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-09-20 12:44:54 +02:00
Sandrine Bailleux 52f6db9e50 User guide: Fix link to Linux master tree
Change-Id: Ia67a4786350c1c2ef55125cd6a318ae6d918c08e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-09-20 10:28:12 +02:00
David Cunado eb19da931c Update dependencies for ARM TF
- Linaro binaries:    18.04
- mbed TLS library:   2.12.0
- FVP model versions: 11.4 build 37

This patch updates the user guide documentation to reflect these
changes to the dependencies.

Change-Id: I454782ca43a0db43aeeef2ab3622f4dea9dfec55
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-09-11 14:36:08 +01:00
Dimitris Papastamos 36044baf08
Merge pull request #1515 from bryanodonoghue/atf-master+linaro-warp7-squash-v4
Atf master+linaro warp7 squash v4
2018-09-05 12:20:10 +01:00
Dimitris Papastamos 05ca725465
Merge pull request #1554 from jts-arm/mbed
Mbed TLS shared heap
2018-09-05 12:19:03 +01:00
Dimitris Papastamos 956c80fc21
Merge pull request #1556 from jts-arm/docs
Fix broken links in documentation
2018-09-05 11:31:19 +01:00
Bryan O'Donoghue b182a5d989 docs: warp7: Add description for the i.MX7 WaRP7 platform
This patch describes the boot-flow and building of the WaRP7 TF-A port.
What it describes is booting and unsigned TF-A.

A very brief section has been added on signing BL2 which is in no-way
comprehensive. For a comprehensive description of the signing process try
the Boundary Devices blog on the matter.

https://boundarydevices.com/high-assurance-boot-hab-dummies/

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04 15:06:01 +01:00
John Tsichritzis af45d640af Fix broken links in documentation
Change-Id: Ic58f88fa4e5fc0004a33357915ff80db30954441
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-09-04 11:28:02 +01:00
John Tsichritzis ba597da7fd Support shared Mbed TLS heap for FVP
This patch introduces the shared Mbed TLS heap optimisation for Arm
platforms. The objective is the Mbed TLS heap to be shared between BL1
and BL2 so as to not allocate the heap memory twice. To achieve that,
the patch introduces all the necessary helpers for implementing this
optimisation. It also applies it for FVP.

Change-Id: I6d85eaa1361517b7490956b2ac50f5fa0d0bb008
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-09-04 10:32:22 +01:00
John Tsichritzis 6d01a46334 Prepare Mbed TLS drivers for shared heap
The Mbed TLS drivers, in order to work, need a heap for internal usage.
This heap, instead of being directly referenced by the drivers, now it
is being accessed indirectly through a pointer. Also, the heap, instead
of being part of the drivers, now it is being received through the
plat_get_mbedtls_heap() function. This function requests a heap from the
current BL image which utilises the Mbed TLS drivers.

Those changes create the opportunity for the Mbed TLS heap to be shared
among different images, thus saving memory. A default heap
implementation is provided but it can be overridden by a platform
specific, optimised implemenetation.

Change-Id: I286a1f10097a9cdcbcd312201eea576c18d157fa
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-09-04 10:32:06 +01:00
Soby Mathew ebf417aa83
Merge pull request #1540 from MISL-EBU-System-SW/marvell-updates-18.09
Marvell updates 18.09
2018-09-04 03:35:54 +01:00
Konstantin Porotchkin c5e0b3b06f docs: marvell: Update build manual
Update build manual
- remove irrelevant platforms and environemnt variables
- add links to BLE and mv_ddr Github repositories

Change-Id: Ie389c61f014751cdc0459b3f78c70ede694d27b8
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-09-02 14:10:47 +03:00
Dimitris Papastamos 7bb907e0d9
Merge pull request #1544 from jwerner-chromium/JW_handle_ea
context_mgmt: Fix HANDLE_EA_EL3_FIRST implementation
2018-08-30 16:09:30 +01:00
Douglas Raillard 0c62883f7e backtrace: Introduce backtrace function
This function diplays the backtrace, the current EL and security state
to allow a post-processing tool to choose the right binary to interpret
the dump.

The output can be fed to GNU addr2line to resolve function names given
an ELF binary compiled with debug information. The "-i" flag is
recommended to improve display in case of inlined functions. The *.dump
files generated during the build process can also be used.

The function works in AArch64 and AArch32. In AArch32 it only works in
A32 mode (without T32 interworking), which is enforced in the Makefile.

Sample output of a backtrace at EL3:

    BACKTRACE: START: function_name
    0: EL3: 0x798
    1: EL3: 0x538
    2: EL3: 0x550
    3: EL3: 0x55c
    4: EL3: 0x568
    5: EL3: 0x5a8
    6: EL3: 0xf4
    BACKTRACE: END: function_name

In order to enable it the new option ENABLE_BACKTRACE must be set to 1.
This option is set to 1 by default only in AArch64 debug builds. As
usual, it can be overridden by the platform makefile and in the build
command line.

Change-Id: Icaff39b0e5188329728be2f3c72b868b2368e794
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2018-08-30 09:21:53 +01:00
Antonio Nino Diaz 8fd9d4d58a Allow manually setting the AArch32 instruction set
At the moment the AArch32 instruction set isn't specified in the command
line, which means that the compiler is free to choose the one it sees
fit. This decision may change between compiler versions, so it is better
to specify it manually.

The build option AARCH32_INSTRUCTION_SET has been introduced for this
reason. This option can be set to T32 or A32 to pass the correct flags
to the compiler.

The current behaviour is to default to T32 due to it's smaller size.

Change-Id: I02297eb1d9404b5868ff7c054fbff9b3cda7fdb6
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-30 09:21:53 +01:00
Julius Werner 24f671f3a9 context_mgmt: Fix HANDLE_EA_EL3_FIRST implementation
This patch fixes a bug in the context management code that causes it to
ignore the HANDLE_EA_EL3_FIRST compile-time option and instead always
configure SCR_EL3 to force all external aborts to trap into EL3. The
code used #ifdef to read compile-time option declared with add_define in
the Makefile... however, those options are always defined, they're just
defined to either 0 or 1, so #if is the correct syntax to check for
them. Also update the documentation to match.

This bug has existed since the Nov 2017 commit 76454abf4 (AArch64:
Introduce External Abort handling), which changed the
HANDLE_EA_EL3_FIRST option to use add_define.

Change-Id: I7189f41d0daee78fa2fcf4066323e663e1e04d3d
Signed-off-by: Julius Werner <jwerner@chromium.org>
2018-08-29 17:16:20 -07:00
Antonio Nino Diaz 870ce3ddd3 libc: Move tf_printf and tf_snprintf to libc
Change their names to printf and snprintf. They are much smaller than
the previous versions we had, which makes them better suited for the
Trusted Firmware.

Change-Id: Ia872af91b7b967c47fce012eccecede7873a3daf
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-22 10:26:05 +01:00
Antonio Nino Diaz 27989a8e34 libc: Introduce files from SCC
Taken from http://git.simple-cc.org/scc/ from the following commit:

67508ad14af314cea2229783d3c084f28c41daf0

Permission has been granted from the author to use them under the
license BSD-3-Clause instead of ISC.

Change-Id: I65c0ce3ab60c49d34a57533af12a74bd7bde88e5
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-22 10:26:05 +01:00
Dimitris Papastamos 61e7c0542e
Merge pull request #1533 from jeenu-arm/mpam
AArch64: Enable MPAM for lower ELs
2018-08-22 10:24:24 +01:00
Dimitris Papastamos f147a8f8a8
Merge pull request #1523 from jts-arm/dsu
DSU erratum 936184 workaround
2018-08-20 09:37:16 +01:00
Jeenu Viswambharan 5f83591880 AArch64: Enable MPAM for lower ELs
Memory Partitioning And Monitoring is an Armv8.4 feature that enables
various memory system components and resources to define partitions.
Software running at various ELs can then assign themselves to the
desired partition to control their performance aspects.

With this patch, when ENABLE_MPAM_FOR_LOWER_ELS is set to 1, EL3 allows
lower ELs to access their own MPAM registers without trapping to EL3.
This patch however doesn't make use of partitioning in EL3; platform
initialisation code should configure and use partitions in EL3 if
required.

Change-Id: I5a55b6771ccaa0c1cffc05543d2116b60cbbcdcd
Co-authored-by: James Morse <james.morse@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-08-20 07:32:19 +01:00
Dimitris Papastamos 6456fe85e4
Merge pull request #1529 from satheesbalya-arm/sb1_2549_fix_dtc_warn
DTC: Add recommended device tree compiler version
2018-08-17 16:00:30 +01:00
John Tsichritzis 8a6771803f DSU erratum 936184 workaround
If the system is in near idle conditions, this erratum could cause a
deadlock or data corruption. This patch applies the workaround that
prevents this.

This DSU erratum affects only the DSUs that contain the ACP interface
and it was fixed in r2p0. The workaround is applied only to the DSUs
that are actually affected.

Link to respective Arm documentation:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm138168/index.html

Change-Id: I033213b3077685130fc1e3f4f79c4d15d7483ec9
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-08-17 10:34:43 +01:00
Sathees Balya 2eadd344ea DTC: Add recommended device tree compiler version
Change-Id: Ice87052e41a24b0ede5610467e12941ae1d886e0
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
2018-08-17 10:31:54 +01:00
John Tsichritzis ef9b68e275 Fix typo in documentation page title
Change-Id: I426ffc8717757e35e556f675162a729ba095b7d5
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-08-15 14:54:40 +01:00
danh-arm d87d524ee4
Merge pull request #1466 from Yann-lms/stm32mp1
Add STMicroelectronics STM32MP1 platform support
2018-07-25 16:05:35 +01:00
danh-arm e16d459daa
Merge pull request #1492 from jts-arm/docs
Reword LOAD_IMAGE_V2 in user guide & fix a typo
2018-07-25 15:23:58 +01:00
Yann Gautier f0958d8444 stm32mp1: Add platform documentation
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2018-07-24 17:18:45 +02:00
danh-arm 790e6c5b96
Merge pull request #1485 from jeenu-arm/ras
Double-fault and fatal error handling support
2018-07-24 14:36:43 +01:00
John Tsichritzis 4901c533d5 Reword LOAD_IMAGE_V2 in user guide & fix a typo
Change-Id: Id2639218dfffec84d8b0fa295d7e896129d4fcd7
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-07-24 14:22:18 +01:00
danh-arm ba0248b52d
Merge pull request #1450 from MISL-EBU-System-SW/marvell-support-v6
Marvell support for Armada 8K SoC family
2018-07-19 17:11:32 +01:00
Jeenu Viswambharan 4431aae973 RAS: Update porting guide with RAS platform handlers
Change-Id: I76cb1d387ab51ee48fa91fd7458c7041b454ceee
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-07-19 10:13:18 +01:00
Konstantin Porotchkin 939e085654 docs: Add Marvell build and porting documents
Change-Id: I341440701b7e5e3555e604dd9d0a356795e6c4fb
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin c0474d5843 marvell: drivers: Add address decoding units drivers
Add address decoding unit drivers for Marvell SoCs.

Address decoding flow and address translation units chart
are located at docs/marvell/misc/mvebu-a8k-addr-map.txt

Change-Id: Id6ce311fa1f4f112df3adfac5d20449f495f71ed
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Antonio Nino Diaz aa49bde8a3 rpi3: Move NS-DRAM out of the protected region
The Non-secure DRAM region shouldn't be protected in the range specified
in the Linux command line with memmap.

This change also increases the size of the Secure DRAM region.

Change-Id: I306e9e443a84b834c99739f54a534a3ca3be2424
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Antonio Nino Diaz 97fb05e1ec rpi3: Switch addresses of kernel and DTB
In the memory map of the documentation the kernel only had 16MiB of
allocated space. This leaves very little room for growth, so the
addresses of the DTB and the kernel have been interchanged.

The documentation has been updated to reflect this change.

Change-Id: Ib6eab69f047fa88561fb755397ce3a0b356c8860
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Antonio Nino Diaz 5e2e024b3d rpi3: Update documentation
Add information about direct Linux kernel boot for kernels that support
PSCI.

Change-Id: I05f76aa36398edabf411cb25a646437af1862e6e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Antonio Nino Diaz 1aad932ce6 rpi3: Add support for the stack protector
It uses the hardware RNG in a similar way as Juno (it gets 128 bits of
entropy and does xor on them).

It is disabled by default.

Change-Id: I8b3adb61f5a5623716e0e8b6799404c68dd94c60
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Antonio Nino Diaz 98967fb14a rpi3: Remove broken support of RESET_TO_BL31
There is no way to boot BL31 at the addresses specified in the platform
memory map unless an extra loader is used at address 0x00000000. It is
better to remove it to prevent confusion. Having it enabled was a bug.

Change-Id: I3229fbc080f5996cff47efce8e799bae94e0d5cb
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Antonio Nino Diaz 64fe343c03 rpi3: Concatenate BL1 and FIP automatically
Add a new default makefile target to concatenate BL1 and the FIP and
generate armstub8.bin. This way it isn't needed to do it manually.

Documentation updated to reflect the changes.

Change-Id: Id5b5b1b7b9f87767db63fd01180ddfea855a7207
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-13 15:27:01 +01:00
Dimitris Papastamos 6e779ace0a
Merge pull request #1476 from grandpaul/paulliu-rpi3-modify-size
rpi3: enlarge SEC_DRAM0_SIZE for optee_test to pass
2018-07-12 11:53:37 +01:00
Ying-Chun Liu (PaulLiu) 8ebf806fc5 rpi3: enlarge SEC_DRAM0_SIZE for optee_test to pass
Running optee_test failed because SEC_DRAM0_SIZE is too small. Previous
is 2 MB. We enlarge it to 11 MB for passing the test. Also we reduce
the NS_DRAM0_SIZE from 13MB to 4MB so that the whole section is still
fit in 16MB.

This commit also modified the document to reflect the changes we've
made in code.

Tested-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
2018-07-12 13:51:35 +08:00
Antonio Nino Diaz d35de55e55 rpi3: Implement simple interrupt routing
Implement minimal interrupt routing functions. All interrupts are
treated as non-secure interrupts to be handled by the non-secure world.

Add note to the documentation about disabling FIQs qhen using OP-TEE
with Linux.

Change-Id: I937096542d973925e43ae946c5d0b306d0d95a94
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-11 21:00:32 +01:00
Dimitris Papastamos 9a93d8ccff
Merge pull request #1460 from robertovargas-arm/clang
Make TF compatible with Clang assembler and linker
2018-07-11 11:13:36 +01:00
Roberto Vargas 4a98f0ef4c Update documentation about how to use clang toolchain
Change-Id: Ie65eb779b048940cf32ed5744ff40610b3c5499d
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-07-11 09:23:07 +01:00
Roberto Vargas 00b7db3038 Add documentation about clang version supported
The user guide didn't contain any information about the
requirements of the clang version needed by TF, which is
at least 4.0.

Change-Id: I1ea120aca0fb2c0950fbeaf6978c654ec277afde
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-07-11 09:20:59 +01:00
Sathees Balya befcbdffc9 Added device-tree-compiler to the list of packages
Change-Id: Ia7800dae52f152b2c3a3b41f1078ab7499d2f4b6
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
2018-07-10 14:49:38 +01:00
Dimitris Papastamos b6c07bbb2e
Merge pull request #1463 from grandpaul/paulliu-rpi3-tbb0
rpi3: Add support for Trusted Board Boot
2018-07-06 13:03:57 +01:00
Dimitris Papastamos 0a15eb9cac
Merge pull request #1465 from Andre-ARM/allwinner/h6-support
allwinner: Add H6 SoC support
2018-07-05 15:34:19 +01:00
Ying-Chun Liu (PaulLiu) ebbdbb1fd6 docs: rpi3: add description for Trusted Board Boot
Add paragraph for how to enable Trusted Board Boot for rpi3

Tested-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
2018-07-05 14:59:05 +08:00
Ying-Chun Liu (PaulLiu) 6a2c3c7fd8 docs: rpi3: fix the size of BL1
For Trusted Board Boot we enlarge the BL1 size from 64k to 128k.

Tested-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
2018-07-05 14:59:02 +08:00
Dimitris Papastamos 5775b9e752
Merge pull request #1461 from antonio-nino-diaz-arm/an/xlat-docs
xlat v2: Update documentation
2018-07-04 15:09:49 +01:00
Andre Przywara bed42a5d28 allwinner: Add Allwinner H6 SoC support
The H6 is Allwinner's most recent SoC. It shares most peripherals with the
other ARMv8 Allwinner SoCs (A64/H5), but has a completely different memory
map.

Introduce a separate platform target, which includes a different header
file to cater for the address differences. Also add the new build target
to the documentation.

The new ATF platform name is "sun50i_h6".

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-07-03 17:06:30 +01:00
Antonio Nino Diaz 5cff8823a7 xlat v2: Update documentation
Update documentation to reflect the current state of the library.

Change-Id: Ic72f90ee322d2ebd6ea7f4296315700d6bc434e6
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-03 14:56:31 +01:00
Andre Przywara 2dde1f5149 allwinner: doc: add missing paragraphs
Add two empty lines to denote the paragraphs properly and improve
readability.

Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-06-28 23:47:30 +01:00
Amit Singh Tomar dab901f83a allwinner: Add BL32 (corresponds to Trusted OS) support
This patch is an attempt to run Trusted OS (OP-TEE OS being one of them) along
side BL31 image.

ATF supports multiple SPD's that can take dispatcher name (opteed for OP-TEE OS)
as an input using the 'SPD=<dispatcher name>' option during bl31 build.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2018-06-28 23:47:30 +01:00
Dimitris Papastamos d48f193d11
Merge pull request #1429 from jeenu-arm/mmu-direct
Enable MMU without stack for xlat v2/DynamIQ
2018-06-27 12:59:47 +01:00
Jeenu Viswambharan 64ee263e20 DynamIQ: Enable MMU without using stack
Having an active stack while enabling MMU has shown coherency problems.
This patch builds on top of translation library changes that introduces
MMU-enabling without using stacks.

Previously, with HW_ASSISTED_COHERENCY, data caches were disabled while
enabling MMU only because of active stack. Now that we can enable MMU
without using stack, we can enable both MMU and data caches at the same
time.

NOTE: Since this feature depends on using translation table library v2,
disallow using translation table library v1 with HW_ASSISTED_COHERENCY.

Fixes ARM-software/tf-issues#566

Change-Id: Ie55aba0c23ee9c5109eb3454cb8fa45d74f8bbb2
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-06-27 11:31:30 +01:00
Soby Mathew 3208edcdfe ARM platforms: Initialize cntfrq for BL1 Firmware update
Currenly the CNTFRQ register and system timer is initialized in BL31 for
use by the normal world. During firmware update, the NS-BL1 or NS-BL2U
may need to access the system timer. Hence this patch duplicates the
CNTFRQ and system timer initialization in BL1 as well.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I1ede78b4ae64080fb418cb93f3e48b26d7b724dc
2018-06-26 15:55:46 +01:00
John Tsichritzis 677ad32cd2 Fix typos in documentation
In the porting guide, there are blue boxes that describe the argument
types and the return type of each function.  A small typo caused some of
these boxes not being properly rendered.

In the user guide, small typos were fixed that caused random text being
unintentionally rendered as bold.  Also, a slight rewording was done in
the section describing the DYN_DISABLE_AUTH flag.

Change-Id: I57303ca609436a82162fa9b42c06b0d5a63da6df
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-06-22 14:15:31 +01:00
Dimitris Papastamos 9dfd755303
Merge pull request #1437 from jeenu-arm/ras-remaining
SDEI dispatch changes to enable RAS use cases
2018-06-22 09:36:59 +01:00
Dimitris Papastamos 826469bc65
Merge pull request #1440 from antonio-nino-diaz-arm/an/xlat-enums
xlat: Remove mmap_attr_t enum type
2018-06-22 09:36:45 +01:00
Dimitris Papastamos 520c9dd4a8
Merge pull request #1427 from b49020/integration
Add support for Socionext Synquacer SC2A11 SoC based Developerbox platform.
2018-06-22 09:36:15 +01:00
Antonio Nino Diaz 3a1b7b108a xlat: Remove mmap_attr_t enum type
The values defined in this type are used in logical operations, which
goes against MISRA Rule 10.1: "Operands shall not be of an inappropriate
essential type".

Now, `unsigned int` is used instead. This also allows us to move the
dynamic mapping bit from 30 to 31. It was an undefined behaviour in the
past because an enum is signed by default, and bit 31 corresponds to the
sign bit. It is undefined behaviour to modify the sign bit. Now, bit 31
is free to use as it was originally meant to be.

mmap_attr_t is now defined as an `unsigned int` for backwards
compatibility.

Change-Id: I6b31218c14b9c7fdabebe432de7fae6e90a97f34
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-06-22 08:36:21 +01:00
Jeenu Viswambharan cdb6ac94ec SDEI: Make dispatches synchronous
SDEI event dispatches currently only sets up the Non-secure context
before returning to the caller. The actual dispatch only happens upon
exiting EL3 next time.

However, for various error handling scenarios, it's beneficial to have
the dispatch happen synchronously. I.e. when receiving SDEI interrupt,
or for a successful sdei_dispatch_event() call, the event handler is
executed; and upon the event completion, dispatcher execution resumes
after the point of dispatch. The jump primitives introduced in the
earlier patch facilitates this feature.

With this patch:

  - SDEI interrupts and calls to sdei_dispatch_event prepares the NS
    context for event dispatch, then sets a jump point, and immediately
    exits EL3. This results in the client handler executing in
    Non-secure.

  - When the SDEI client completes the dispatched event, the SDEI
    dispatcher does a longjmp to the jump pointer created earlier. For
    the caller of the sdei_dispatch_event() in particular, this would
    appear as if call returned successfully.

The dynamic workaround for CVE_2018_3639 is slightly shifted around as
part of related minor refactoring. It doesn't affect the workaround
functionality.

Documentation updated.

NOTE: This breaks the semantics of the explicit dispatch API, and any
exiting usages should be carefully reviewed.

Change-Id: Ib9c876d27ea2af7fb22de49832e55a0da83da3f9
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-06-21 16:15:23 +01:00
Jeenu Viswambharan af2c9ecdf1 SDEI: Allow platforms to define explicit events
The current macros only allow to define dynamic and statically-bound
SDEI events. However, there ought be a mechanism to define SDEI events
that are explicitly dispatched; i.e., events that are dispatched as a
result of a previous secure interrupt or other exception

This patch introduces SDEI_EXPLICIT_EVENT() macro to define an explicit
event. They must be placed under private mappings. Only the priority
flags are allowed to be additionally specified.

Documentation updated.

Change-Id: I2e12f5571381195d6234c9dfbd5904608ad41db3
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-06-21 16:15:23 +01:00
Dimitris Papastamos e960518854
Merge pull request #1428 from jeenu-arm/mbedtls
Move to mbedtls-2.10.0 tag
2018-06-21 14:35:54 +01:00
Sumit Garg 150c38e84d synquacer: Add platform makefile and documentation
Add Makefile and plaform definations file.
My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces
I've taken from their earlier work regarding build and deploy steps for
Developerbox based on Synquacer SoCs. They deserve much of the credit
for this work although, since I assembled and tested things, any blame
is probably mine.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Daniel Thompson <daniel.thompson@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-06-21 14:18:37 +05:30
Dimitris Papastamos 3caa841d9c
Merge pull request #1403 from glneo/for-upstream-k3
TI K3 platform support
2018-06-20 16:37:01 +01:00
Dimitris Papastamos a125014bdb
Merge pull request #1413 from grandpaul/paulliu-rpi3-0
rpi3: BL32 optee support
2018-06-20 16:34:10 +01:00
Nishanth Menon 1841c533c9 ti: k3: Setup initial files for platform
Create the baseline Makefile, platform definitions file and platform
specific assembly macros file. This includes first set of constants
for the platform including cache sizes and linker format and a stub for
BL31 and the basic memory layout

K3 SoC family of processors do not use require a BL1 or BL2 binary,
since such functions are provided by an system controller on the SoC.
This lowers the burden of ATF to purely managing the local ARM cores
themselves.

Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-06-19 11:41:25 -05:00
Dimitris Papastamos d135ad7884
Merge pull request #1410 from Anson-Huang/master
Add NXP's i.MX8QX and i.MX8QM SoC support
2018-06-19 15:10:23 +01:00
Ying-Chun Liu (PaulLiu) 3d4642343f rpi3: update documentation for OP-TEE support
Describe how to use BL32 build variable to load OP-TEE into FIP.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
2018-06-19 16:40:22 +08:00
Dimitris Papastamos ac0197d9d5
Merge pull request #1400 from Andre-ARM/allwinner/v1
Allwinner platform support
2018-06-19 09:16:07 +01:00
Anson Huang baa7650bf8 Support for NXP's i.MX8QM SoC
NXP's i.MX8QM is an ARMv8 SoC with 2 clusters, 2 Cortex-A72
cores in one cluster and 4 Cortex-A53 in the other cluster,
and also has system controller (Cortex-M4) inside, documentation
can be found in below link:

https://www.nxp.com/products/processors-and-microcontrollers/
applications-processors/i.mx-applications-processors/i.mx-8-processors:IMX8-SERIES

This patch adds support for booting up SMP linux kernel (v4.9).

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-19 10:24:32 +08:00
Anson Huang 0bc1830928 Support for NXP's i.MX8QX SoC
NXP's i.MX8QX is an ARMv8 SoC with 4 Cortex-A35 cores and
system controller (Cortex-M4) inside, documentation can
be found in below link:

https://www.nxp.com/products/processors-and-microcontrollers/
applications-processors/i.mx-applications-processors/i.mx-8-processors:IMX8-SERIES

This patch adds support for booting up SMP linux kernel (v4.9).

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-19 10:24:32 +08:00
Jeenu Viswambharan d25b527c88 Move to mbedtls-2.10.0 tag
To build with the new release, we pick couple of more files from mbedTLS
library.

Change-Id: I77dfe5723284cb26d4e5c717fb0e6f6dd803cb6b
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-06-18 09:35:29 +01:00
Samuel Holland 64b3d9d88e allwinner: Add Allwinner A64 support
The Allwinner A64 SoC is quite popular on single board computers.
It comes with four Cortex-A53 cores in a singe cluster and the usual
peripherals for set-top box/tablet SoC.

The ATF platform target is called "sun50i_a64".

[Andre: adapted to amended directory layout, removed unneeded definitions ]

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-06-15 11:45:24 +01:00
Dimitris Papastamos 1ebdbe79c7
Merge pull request #1414 from antonio-nino-diaz-arm/an/fix-rpi3-doc
rpi3: Fix kernel boot documentation
2018-06-14 14:40:24 +01:00
Daniel Boulby 9bd5a4ce1e Correct ordering of log levels in documentation
Changed the ordering of the log levels in the documentation to
mate the code

Change-Id: Ief1930b73d833fdf675b039c98046591c0c264c1
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-06-14 10:27:03 +01:00
Antonio Nino Diaz 2d8f831fb2 rpi3: Fix kernel boot documentation
The order of the arguments of memmap was swapped. The old command was
reserving 256 MiB from the 16 MiB barrier, it should be reserving only
16 MiB at the 256 MiB barrier.

It worked because the memory used by the Trusted Firmware was reserved
anyway.

Change-Id: I3fefcfc0105ecf05ba5606517bc3236f4eb24ceb
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-06-13 15:05:53 +01:00
Dimitris Papastamos 42be6fc57e Adjust BL2_AT_EL3 memory layout
For the BL2_AT_EL3 configuration, move BL2 higher up to make more
space for BL31.  Adjust the BL31 limit to be up to BL2 base.  This is
because BL2 is always resident for the BL2_AT_EL3 configuration and
thus we cannot overlay it with BL31.

Change-Id: I71e89863ed48f5159e8b619f49c7c73b253397aa
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-06-11 14:18:06 +01:00
Dimitris Papastamos 4b55732583
Merge pull request #1404 from soby-mathew/sm/bl_layout_change
ARM platforms: Change memory layout and update documentation
2018-06-07 14:49:25 +01:00
Soby Mathew 0f57fabf7f docs: Firmware design update for BL memory layout
This patch updates the firmware design guide for the BL memory
layout change on ARM platforms.

Change-Id: Icbfe7249484bb8b4ba3c94421172d42f27605c52
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-06-07 12:26:19 +01:00
Soby Mathew c099cd3942 ARM platforms: Move BL31 below BL2 to enable BL2 overlay
The patch changes the layout of BL images in memory to enable
more efficient use of available space. Previously BL31 was loaded
with the expectation that BL2 memory would be reclaimed by BL32
loaded in SRAM. But with increasing memory requirements in the
firmware, we can no longer fit BL32 in SRAM anymore which means the
BL2 memory is not reclaimed by any runtime image. Positioning BL2
below BL1-RW and above BL31 means that the BL31 NOBITS can be
overlaid on BL2 and BL1-RW.

This patch also propogates the same memory layout to BL32 for AArch32
mode. The reset addresses for the following configurations are also
changed :
   * When RESET_TO_SP_MIN=1 for BL32 in AArch32 mode
   * When BL2_AT_EL3=1 for BL2

The restriction on BL31 to be only in DRAM when SPM is enabled
is now removed with this change. The update to the firmware design
guide for the BL memory layout is done in the following patch.

Change-Id: Icca438e257abe3e4f5a8215f945b9c3f9fbf29c9
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-06-07 12:26:19 +01:00
Dimitris Papastamos d003b19093
Merge pull request #1392 from dp-arm/dp/cve_2018_3639
Implement workaround for CVE-2018-3639 on Cortex A57/A72/A73 and A75
2018-05-29 09:28:05 +01:00
Dimitris Papastamos edcd266e6a
Merge pull request #1395 from antonio-nino-diaz-arm/an/spm-refactor
SPM: Refactor codebase
2018-05-25 09:47:11 +01:00
Antonio Nino Diaz e829a3796f plat/arm: SPM: Force BL31 to DRAM when SPM is used
BL31 is running out of space, and the use-case of SPM doesn't require it
to be in SRAM. To prevent BL31 from running out of space in the future,
move BL31 to DRAM if SPM is enabled.

Secure Partition Manager design document updated to reflect the changes.

Increased the size of the stack of BL31 for builds with SPM.

The translation tables used by SPM in Arm platforms have been moved back
to the 'xlat_tables' region instead of 'arm_el3_tzc_dram'. Everything is
in DRAM now, so it doesn't make sense to treat them in a different way.

Change-Id: Ia6136c8e108b8da9edd90e9d72763dada5e5e5dc
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-05-24 09:15:03 +01:00
Dimitris Papastamos fe007b2e15 Add support for dynamic mitigation for CVE-2018-3639
Some CPUS may benefit from using a dynamic mitigation approach for
CVE-2018-3639.  A new SMC interface is defined to allow software
executing in lower ELs to enable or disable the mitigation for their
execution context.

It should be noted that regardless of the state of the mitigation for
lower ELs, code executing in EL3 is always mitigated against
CVE-2018-3639.

NOTE: This change is a compatibility break for any platform using
the declare_cpu_ops_workaround_cve_2017_5715 macro.  Migrate to
the declare_cpu_ops_wa macro instead.

Change-Id: I3509a9337ad217bbd96de9f380c4ff8bf7917013
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-05-23 12:45:48 +01:00
Dimitris Papastamos b8a25bbb0b Implement static workaround for CVE-2018-3639
For affected CPUs, this approach enables the mitigation during EL3
initialization, following every PE reset. No mechanism is provided to
disable the mitigation at runtime.

This approach permanently mitigates the entire software stack and no
additional mitigation code is required in other software components.

TF-A implements this approach for the following affected CPUs:

*   Cortex-A57 and Cortex-A72, by setting bit 55 (Disable load pass store) of
    `CPUACTLR_EL1` (`S3_1_C15_C2_0`).

*   Cortex-A73, by setting bit 3 of `S3_0_C15_C0_0` (not documented in the
    Technical Reference Manual (TRM)).

*   Cortex-A75, by setting bit 35 (reserved in TRM) of `CPUACTLR_EL1`
    (`S3_0_C15_C1_0`).

Additionally, a new SMC interface is implemented to allow software
executing in lower ELs to discover whether the system is mitigated
against CVE-2018-3639.

Refer to "Firmware interfaces for mitigating cache speculation
vulnerabilities System Software on Arm Systems"[0] for more
information.

[0] https://developer.arm.com/cache-speculation-vulnerability-firmware-specification

Change-Id: I084aa7c3bc7c26bf2df2248301270f77bed22ceb
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-05-23 12:45:48 +01:00
Dimitris Papastamos 0d018306d4
Merge pull request #1386 from soby-mathew/sm/dyn_bl31
Extend dynamic configuration
2018-05-23 12:45:13 +01:00
Soby Mathew 7e8686d91e Docs: Update user guide for Dynamic Config on FVP
From TF-A v1.5, FVP supports loading the kernel FDT through
firmware as part of dynamic configuration feature. This means
that the FDT no longer needs to be loaded via Model parameters.
This patch updates the user guide to reflect the same.

Change-Id: I79833beeaae44a1564f6512c3a473625e5959f65
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-05-21 09:56:11 +01:00
Soby Mathew 209a60cca5 Allow disabling authentication dynamically
This patch allows platforms to dynamically disable authentication of
images during cold boot. This capability is controlled via the
DYN_DISABLE_AUTH build flag and is only meant for development
purposes.

Change-Id: Ia3df8f898824319bb76d5cc855b5ad6c3d227260
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-05-18 12:26:37 +01:00
Dimitris Papastamos f859a5dd28
Merge pull request #1382 from sandrine-bailleux-arm/topics/sb/fix-doc
Fix doc for bl31_plat_get_next_image_ep_info()
2018-05-16 14:26:52 +01:00
Dimitris Papastamos dcf1a04e3b
Merge pull request #1381 from antonio-nino-diaz-arm/an/kernel-boot
plat/arm: Introduce ARM_LINUX_KERNEL_AS_BL33 build option
2018-05-16 14:26:28 +01:00
Sandrine Bailleux 1ec1ebf782 Fix doc for bl31_plat_get_next_image_ep_info()
In the porting guide, fix the function name and the argument type to
reflect the code.

Change-Id: Iac8d69af403194de5586bc0d5890da531e3c8da2
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-05-14 14:26:42 +02:00
Antonio Nino Diaz 32412a8a6b Replace bootwrapped kernel instructions from User Guide
The instructions to boot the bootwrapped kernel were outdated.

Also, the bootwrapped kernel boot flow isn't really useful. It was meant
to be a replacement for the Trusted Firmware-A, not to be used as the next
step during boot.

The instructions have been removed in favour of the new build option
ARM_LINUX_KERNEL_AS_BL33. This new system directly boots the Linux
kernel from BL31, and requires RESET_TO_BL31 to be 1. Also, the kernel
has to be preloaded in memory, so PRELOADED_BL33_BASE has to be set to its
address. This way, the runtime services of the Trusted Firmware-A are
available for the kernel in the least possible amount of time.

This new system requires the DTB to be patched so that the kernel knows
where the ramdisk is. A short script to add this information to the DTB
has been added to the User Guide. The information related to it can be
found in the following file in the Linux kernel tree:
``Documentation/devicetree/bindings/chosen.txt``

Change-Id: Ide135580959e09f6aa8e4425f37ea55d97439178
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-05-14 09:12:34 +01:00