* changes:
docs: armv8-R aarch64 fvp_r documentation
fvp_r: load, auth, and transfer from BL1 to BL33
chore: fvp_r: Initial No-EL3 and MPU Implementation
fvp_r: initial platform port for fvp_r
This patch adds the basic CPU library code to support the Hayes CPU
in TF-A. This CPU is based on the Klein core so that library code
has been adapted for use here.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If0e0070cfa77fee8f6eebfee13d3c4f209ad84fc
Adding load, authentication, and transfer functionality from FVP R BL1 to
BL33, which will be the partner runtime code.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I293cad09739dacac0d20dd57c1d98178dbe84d40
For v8-R64, especially R82, creating code to run BL1 at EL2, using MPU.
Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I439ac3915b982ad1e61d24365bdd1584b3070425
Creating a platform port for FVP_R based on the FVP platform.
Differences including only-BL1, aarch64, Secure only, and EL2 being the
ELmax (No EL3).
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I1283e033fbd4e03c397d0a2c10c4139548b4eee4
Function polling_with_timeout() returns last value from polled register
on failure and zero on success. So set "ret" variable to error code
-ETIMEDOUT on error like it is done in other functions.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I16cac81bbcbe2113e139722dc0e8fc2b85428d1b
Subroutines in power functions may fail. So propagate failures from
subroutines back to the caller of power function with appropriate error
code in return value.
Function polling_with_timeout() returns last value from polled register
on failure and zero on success. So return -ETIMEDOUT on error from power
functions like it is doing Marvell comphy-cp110 driver.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6c709c0c9616ab26829616a42a85b713f314b201
Physical address has to be stored in 64-bit data type as Armada 3720 is
64-bit platform. Driver already uses uintptr_t type for this purpise.
Change type of 'offset' variables in mvebu_a3700_comphy_usb3_power_on()
and mvebu_a3700_comphy_sgmii_power_on() / off() functions to uintptr_t
as in this variable is stored physical address of registers.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I69581714f8899d21cc1a27005747708f0f1cd933
Parameter 'comphy_index' is not used and parameter 'mode' is used only
to check if speed is 1 Gbps or not.
Remove parameter 'comphy_index' and instead of 32-bit variable 'mode',
pass only boolean value which represents 1 Gbps speed.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I018d158f689ddf7d1f57003717d709c00d988fba
For code cleanup add two helper functions comphy_sata_set_indirect() and
comphy_usb_set_indirect() for SATA and USB 3.0 modes and remove additional
'mode' argument which is not needed anymore.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I23146f569db318dbaed5d411d7d175abf6efff85
The 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an
explicit write to clear it for hotplug and idle to function correctly.
So add Neoverse N2 CPU specific handler in platform reset handler to
clear the CORE_PWRDN_EN bit.
Signed-off-by: shriram.k <shriram.k@arm.com>
Change-Id: If3859447410c4b8e704588993941178fa9411f52
The 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an
explicit write to clear it for hotplug and idle to function correctly.
So add Neoverse V1 CPU specific handler in platform reset handler to
clear the CORE_PWRDN_EN bit.
Signed-off-by: shriram.k <shriram.k@arm.com>
Change-Id: I56084c42a56c401503a751cb518238c83cfca8ac
Currently the SP package loading mechanism is only enabled when S-EL2
SPMC is selected. Remove this limitation.
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Change-Id: I5bf5a32248e85a26d0345cacff7d539eed824cfc
Update UUID to little endian:
The SPMC expects a little endian representation of the UUID as an array
of four integers in the SP manifest.
Add managed exit field and cosmetic comments updates.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Icad93ca70bc27bc9d83b8cf888fe5f8839cb1288
The UUID field in SP manifest DTS is represented as an array of four
integers that the SPMC consumes using the little endian representation.
The reason is that those values are directly mapped to the SMCCC section
5.3 recommendation and the way they are exposed to the
FFA_PARTITION_INFO_GET interface.
Per [1] TF-A build flow expects a big endian representation of the UUID
so the sp_mk_generator script is updated to accommodate this conversion.
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9563
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I7c7b295225e23ea64f49170e27d97442b289703b
CIRQ software reset can be used on all platforms, so we remove
CIRQ_NEED_SW_RESET in mt_cirq_sw_reset to enable software reset.
BUG=b:192200380, b:201035723
Signed-off-by: Pan Gao <gtk_pangao@mediatek.com>
Change-Id: Id53ea099ae566bf2a573fca866bd10c60429bd5a
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.
BUG=b:192429713
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I02c6c862b6217bc84c83a09b533bd53ec19b06f7
FEAT_HCX adds the extended hypervisor configuration register (HCRX_EL2)
and access to this register must be explicitly enabled through the
SCR_EL3.HXEn bit. This patch adds a new build flag ENABLE_FEAT_HCX to
allow the register to be accessed from EL2.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ibb36ad90622f1dc857adab4b0d4d7a89456a522b
* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls1028ardb board support
feat(plat/nxp/ls1028a): add ls1028a soc support
feat(plat/nxp/common): define default SD buffer
feat(driver/nxp/xspi): add MT35XU02G flash info
feat(plat/nxp/common): add SecMon register definition for ch_3_2
feat(driver/nxp/dcfg): define RSTCR_RESET_REQ
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
feat(plat/nxp/common): define default PSCI features if not defined
feat(plat/nxp/common): define common macro for ARM registers
feat(plat/nxp/common): add CCI and EPU address definition
Cortex-A710 erratum 2083908 is a Cat B erratum that applies to
revision r2p0 and is still open. The workaround is to set
CPUACTLR5_EL1[13] to 1.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I876d26a7ac6ab0d7c567a9ec9f34fc0f952589d8
Function mvebu_a3700_comphy_sata_power_off() uses comphy_mode parameter
only for extracting mode bits. Mode is always COMPHY_SATA_MODE, so
there is no need to pass comphy_mode parameter to this function. Use
directly COMPHY_SATA_MODE in mvebu_a3700_comphy_sata_power_off().
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ib6b7c2bf62c1ef4d8a6af240c08696d5cd506b14
The LS1028A reference design board (RDB) is a computing,
evaluation, and development platform that supports industrial
IoT applications, human machine interface solutions, and
industrial networking.
It supports the following features:
1. Layerscape LS1028A dual-core processor based on Cortex-A72
at 1.3 GHz.
2. 4 GB DDR4 SDRAM w/ECC
3. Support Ethernet:
1) x1 RJ45 connector for 1Gbps Ethernet support w/TSN, 1588
2) x4 RJ45 connector for 1Gbps Ethernet switch support w/TSN,
1588 (QSGMII)
3. With Basic Peripherals and Interconnect
2x M.2 Type E slots with PCIe Gen 3.0 x1
1x M.2 Type B slot with SATA 3.0 (resistor mux with 1 Type E slot)
1x Type A USB 3.0 super-speed port
1x Type C USB 3.0 super-speed port
1x DisplayPort interface
2x DB9 RS232 serial ports
2x DB9 CAN interfaces
1x 3.5 mm audio out
2x MikroBUS™ sockets
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Change-Id: I48ee254a488ae4af227641da3875a1e9a63a720c
The QorIQ LS1028A processor integrates two 64-bit ARM Cortex-A72
cores with a GPU and LCD controller, as well as a TSNenabled
Ethernet port and a TSN-enabled switch with four external ports.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Change-Id: I9f65c6af5db7e20702828cd208290c1b43a54941
Change the fdt_get_rcc_node function to static, as it is used only in
stm32mp_clkfunc.c file; it is only a cleanup change without functional
modification.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ib4ef110f6f1b16dbaa727a065e40275d3cf58a73
In BL32, only skip UART initialization if UART enable bit is set.
Due to patch [1], a reset of UART is done in crash console init.
In this case, UART should then be reconfigured.
[1] 7fa2e96e1 ("stm32mp1: add UART reset in crash console init")
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I650d4c387b60dd74b780e6f3adfd629ea44f5834
Add the reset set/clear sequence at the beginning of the function
plat_crash_console_init(). If not done, there is a risk that the UART
is in a bad state and will not be able to print correct characters.
Change-Id: Id31e28773d6c4f26f16d3569d1e3c5aa0e26e039
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The file is first generated with the peripheral spirit XML file.
And then we add some common definition, to ease driver development.
Change-Id: I4c222cf006caf27cda6da044eaf184ce66bb1442
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Further information such as boot instance are sent over backup
registers. In order to guarantee direct access to backup registers
in uboot, we will keep the RTC clock enabled.
Change-Id: I16572d422bfebbf39190a87db8046df486ce91c8
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
When RTC clock source is HSE, the RTCDIV is not taken into account.
Change-Id: I1613b638e8932c03f3349adb01e13f5294a3bf5d
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
The clksrc value contains the RCC register address and the clock
source number. When applying the clock source, we should filter out
the RCC register address from the given value.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4345b03de7b9afd1df78df4131431cf1eb43ec17
On most of SPI NAND, the read id command needs a dummy byte,
except GIGADEVICE SPI NAND that needs an address.
To be compliant with all memories providers, the first byte returns
by the READ_ID command is not relevant (garbage).
Change-Id: Ife74ccab333dd1a04799abe230d3f07fa6ea1edb
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
This patch checks that the SPI NAND parameters needed by
the framework have been set before starting to read data.
Change-Id: I17b36606701c44864dcf1783f810da5c8cbf88f2
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS EL
feat(trf): initialize trap settings of trace filter control registers access
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
feat(sys_reg_trace): initialize trap settings of trace system registers access
feat(trbe): enable access to trace buffer control registers from lower NS EL
feat(trbe): initialize trap settings of trace buffer control registers access
Bipin Ravi
Joanna Farley
johpow01
laurenw-arm
Gary Morrison
Madhukar Pappireddy
Pali Rohár
shriram.k
Olivier Deprez
Tinghan Shen
Manish Pandey
Balint Dobszay
Pan Gao
Rex-BC Chen
nayanpatel-arm
Jiafei Pan
Patrick Delaunay
Saurabh Gorecha
Yann Gautier
Yann Gautier
Lionel Debieve
Gabriel Fernandez
Christophe Kerello