Recently upstreamed changes to OP-TEE mean that it is possible for OP-TEE
to provide a DTB overlay directly to subsequent boot stages thus negating
the requirement to bundle a DTB in the FIP.
This patch switches off the dependency on the DTB in the FIP descriptor
instead we will provide the necessary data as an overlay from OP-TEE.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
This patch adds NXP i.MX8 SoCs' build info SIP support for easy debug.
With this function enabled, TF-A's commit hash can be showed in u-boot
debug console when booting up, when there is any issue which could be
related to TF-A, users can use the commit hash value to easily identify
which commit introduces the issue.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
For NXP's i.MX8 SoCs with system controller inside, thermal sensors
are maintained by SCFW, Linux needs to call SMC to trap to TF-A for
thermal alarm operation etc. by calling SCFW API.
This patch adds temperature alarm SIP service support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
For NXP's i.MX8 SoCs with system controller inside, OTP is
maintained by SCFW, Linux needs to call SMC to trap to TF-A
for OTP read/write etc. operations by calling SCFW API.
This patch adds OTP SIP service support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of misc functions like temperature alarm, dma etc., other
Cortex-A clusters can send out command via MU (Message Unit) to
system controller for misc operation etc..
This patch adds misc IPC(inter-processor communication) support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
On i.MX8QM/i.MX8QX with system controller inside, the wakeup
source is managed in SCFW(system controller firmware), if the
wakeup source is belonged to system controller partition, then
before Linux suspend, the wakeup source should be set to
SC_PM_WAKE_SRC_SCU, and if the wakeup source is belonged to
Cortex-A partition, the wakeup source should be set to
SC_PM_WAKE_SRC_IRQSTEER, so need to add wakeup source SIP runtime
service to get Linux kernel's wakeup source and set the correct
wakeup source for system controller.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
On i.MX8QM/i.MX8QX with system controller inside, the CPU's clock
rate is managed by SCFW(system controller firmware) and can ONLY be
changed from secure world, so SIP runtime service is needed for
setting CPU's clock rate, this patch adds cpu-freq SIP runtime service
support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
On i.MX8QM/i.MX8QX with system controller inside, the SRTC is
managed by SCFW(system controller firmware) and some functions
like setting SRTC's time etc. can ONLY be requested from secure
world, so SIP runtime service is needed for such kind of operations,
this patch adds SRTC SIP runtime service support for i.MX8QM and
i.MX8QX.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of timer management, including watchdog, srtc and system
counter etc., other clusters like Cortex-A35 can send out command
via MU (Message Unit) to system controller for timer operation.
This patch adds timer IPC(inter-processor communication) support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
In case if `RPI3_PRELOADED_DTB_BASE` isn't defined explicitly with
proper pre-loaded DTB address, `add_define` macro defined in
`make_helpers/build_macros.mk` still supplies this definition to the
compiler like `-DRPI3_PRELOADED_DTB_BASE`, and it's obviously is set to
default value 1.
This simply leads to the wrong `MAP_NS_DTB` region definition (base_va
is set `0x1` instead of `0x00010000`) in `plat/rpi3/rpi3_common.c`:
Which causes aligment check to fail in `mmap_add_region_check()`:
VERBOSE: base_pa: 0x00000001, base_va: 0x00000001, size: 0x00010000
...
ERROR: mmap_add_region_check() failed. error -22
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
This patch removes unused type conversions as all the relevant macros
now use U()/ULL(), making these explicit typecasts unnecessary.
Change-Id: I01fb534649db2aaf186406b1aef6897662b44fe3
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
This patch enables L2 error correction and parity protection
for Tegra210 on boot and exit from suspend. The previous bootloader
sets the boot parameter, indicating ECC reporting, only for B01 SKUs.
Change-Id: I6927884d375a64c69e2f1e9aed85f95c5e3cb17c
Signed-off-by: Sam Payne <spayne@nvidia.com>
This patch skips the BTB invalidate workaround for Tegra210-B01 chips, as
they have already been fixed in the hardware. To allow the .S file to
include macros, add proper guards to tegra_platform.h.
Change-Id: I0826d3c54faeffc9cb0709331f47cbdf25d4b653
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Set MC Clients ordering as per the clients needs(ordered, BW, ISO/non-ISO)
based on the latest info received from HW team as a part of BW issues debug.
SMMU Client config register are obsolete from T186. Clean up the unnecessary
register definitions and programming of these registers.
Cleanup unnecessary macros as well.
Change-Id: I0d28ae8842a33ed534f6a15bfca3c9926b3d46b2
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
This patch memmaps all the IRAM memory banks during boot. The BPMP
firmware might place the channels in any of the IRAMs, so it is better
to map all the banks to avoid surprises.
Change-Id: Ia009a65d227ee50fbb23e511ce509daf41b877ee
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch fixes the logic to check if Atomics hardware block is powered
on during boot
Reported by: Peter De Schrijver <pdeschrijver@nvidia.com>
Change-Id: I4a6521bcee37225d1402321151c48fa631776b8a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch updates the macros to include the newly added IRAM
memory apertures.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I931daa310d738e8bf966f14e11d0631920e9bdde
Main fixes:
Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
Force operands of an operator to the same type category [Rule 10.4]
Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]
Change-Id: I4840c3122939f736113d61f1462af3bd7b0b5085
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Main fixes:
Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
convert object type to match the type of function parameters
[Rule 10.3]
Force operands of an operator to the same type category [Rule 10.4]
Fix implicit widening of composite assignment [Rule 10.6]
Change-Id: I5840a07f37beefc3326ac56d0b4a4701602bd8a8
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
This patch removes unwanted error prints from the MCE command
handler, to reduce the code complexity for this function.
Tested with 'pmccabe'
Change-Id: I375d289db1df9e119eeb1830210974457c8905a4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch removes support for the SC8 power state as the feature is no
longer required for Tegra186 projects.
Change-Id: I622a5ddcffe025b9b798801d09bbb856853befd7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Main fixes:
* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses [Rule 20.7]
* Added explicit casts (e.g. 0U) to integers in order for them
to be compatible with whatever operation they're used in [Rule
10.1]
* Fix implicit widening of composite assignment [Rule 10.6]
Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Main fixes:
Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
Force operands of an operator to the same type category [Rule 10.4]
Voided non c-library functions whose return types are not used [Rule 17.7]
Change-Id: I758e7ef6d45dd2edf4cd5580e2af15219246e75c
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
* EKS blob size was not passed by as a boot parameter
earlier. Its being passed now
* If EKS value sent by bootloader is non-zero
update the boot parameter from default value to the argument
passed by bootloader
Change-Id: I65a3091bd2c1c908cc9e81c0aab6489cab02c098
Signed-off-by: Akshay Sharan <asharan@nvidia.com>
DRBG must be initialized to guarantee SRK has a random
value during suspend. This patch add a sequence to generate
an SRK on boot and during resume for SE1 and SE2. This SRK
value is not saved to PMC scratch, and should be overwitten
during atomic suspend.
Change-Id: Id5e2dc74a1b462dd6addaec1709fec46083a6e1c
Signed-off-by: Sam Payne <spayne@nvidia.com>
This patch adds the driver to communicate with the BPMP processor
for power management use cases. BPMP controls the entry into cluster
and system power states. The Tegra210 platform port queries the BPMP
to calculate the target state for the cluster. In case BPMP does not
allow CCx entry, the core enters a power down state.
Change-Id: I9c40aef561607a0b02c49b7f8118570eb9105cc9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch fixes MISRA defects for the MCE driver.
* Using logical NOT for bool type function
* Using MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS replace
MPIDR_CLUSTER_MASK
Change-Id: I97e96f172a3c1158646a15a184c273c53a103d63
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
This patch uses int32_t to replace ints, to fix Rule 4.6 of the
MISRA standard.
Change-Id: I20ac6185929eced684b43da3ef1f8cd5fbddc83d
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds (void) for unused function parameters to
fix Rule 2.7 of the MISRA standard.
Change-Id: Ibc3f10b3bfe73363383b4c28413ab8d99fbc8c89
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds the implementation of the SE atomic context save
sequence. The atomic context-save consistently saves to the TZRAM
carveout; thus there is no need to declare context save buffer or
map MMU region in TZRAM for context save. The atomic context-save
routine is responsible to validate the context-save progress
counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error
status to ensure the context save procedure complete successfully.
Change-Id: Ic80843902af70e76415530266cb158f668976c42
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Main fixes:
* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses [Rule 20.7]
* Added explicit casts (e.g. 0U) to integers in order for them
to be compatible with whatever operation they're used in [Rule
10.1]
* Fix implicit widening of composite assignment [Rule 10.6]
Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds capability to read the boot flag to enable L2 ECC
and Parity Protection bit for the Cortex-A57 CPUs. The previous
bootloader sets this flag value for the platform.
* with some coverity fix:
MISRA C-2012 Directive 4.6
MISRA C-2012 Rule 2.5
MISRA C-2012 Rule 10.3
MISRA C-2012 Rule 10.4
Change-Id: Id7303bbbdc290b52919356c31625847b8904b073
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch sets up the clock for the UART console, for real Silicon
and FPGA platforms. FPGA platforms run the UART clock source at
13MHz, whereas the clock cource runs at 408MHz for real silicon.
Change-Id: Ibfd99df032ec473f29e636e597cfc95a0f580598
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds helper functions to find out the chip ID of the
Tegra SoC.
Change-Id: Ia3901dc7cdf77d8c23884d1ed38a80dba6a8afde
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
The platform code generates the power domain tree. The handler to
retrieve the tree should also reside in the platform code.
This patch moves the plat_get_power_domain_tree_desc() to the
individual platforms.
Change-Id: Iaafc83ed381d83129501111ef655e3c58a8a553f
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds support for simulation platforms as well as
fixes issues flagged by the MISRA scans.
Main MISRA fixes:
* Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
* Fix return type doesn't match the function type [Rule 10.3]
* Use single return point instead of multiple [Rule 15.5]
* Change return type for the tegra_platform_is_x handlers to bool
Change-Id: I871b7c37b22942f6c0c2049c14cc626d4a24d81c
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Enable the deprecated SPM framework for the SynQuacer platform.
It involves creating a memory layout in secure DRAM, and wiring
up the SPM infrastructure so that the secure partition payload
that is loaded into this region by the SCP firmware is dispatched
appropriately.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
The logic that initializes the BL32 entry point data structure
should only be executed if we are in fact loading OP-TEE, and
not if BL32_BASE is set for other reasons (i.e., when enabling
SPM)
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Corrects typos in core code, documentation files, drivers, Arm
platforms and services.
None of the corrections affect code; changes are limited to comments
and other documentation.
Change-Id: I5c1027b06ef149864f315ccc0ea473e2a16bfd1d
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
From now on, platform_def.h must include any header with definitions that
are platform-specific (like arm_def.h) and the included headers mustn't
include back platform_def.h, and shouldn't be used by other files. Only
platform_def.h should be included in other files. This will ensure that all
needed definitions are present, rather than needing to include all the
headers in all the definitions' headers just in case.
This also prevents problems like cyclic dependencies.
Change-Id: I9d3cf4d1de4b956fa035c79545222697acdaf5ca
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
The definitions in bl1/bl1_private.h and bl2/bl2_private.h are useful for
platforms that may need to access them.
Change-Id: Ifd1880f855ddafcb3bfcaf1ed4a4e0f121eda174
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
With DEBUG_CONSOLE enabled, build will fail for imx8mq platform:
./build/imx8mq/release/bl31/imx8mq_bl31_setup.o:
In function `bl31_early_platform_setup2':
imx8mq_bl31_setup.c:(.text.bl31_early_platform_setup2+0x40):
undefined reference to `console_uart_register'
Makefile:741: recipe for target 'build/imx8mq/release/bl31/bl31.elf' failed
make: *** [build/imx8mq/release/bl31/bl31.elf] Error 1
Besides, the .console_flush callback needs to be added to avoid
panic when debug mode is enabled, since the console_flush() will
call it without checking whether the function callback is valid.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Current lpuart driver does NOT implement .console_flush callback,
if debug console is enabled, the console_flush() will call the
undefined .console_flush callback(NULL) for lpuart and leak to
panic, this patch adds .console_flush callback to make lpuart work
for debug mode.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
It is cleaner to use the same number of tables regardless of whether
OP-TEE is used or not. This doesn't result in a significant memory
usage increase.
Change-Id: I38bcaa3f2f197c0a352153117592749f189a265c
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
pm_service ipi functions can be used by other xilinx
platforms. So move it to common directory. Also change
node_id member type in pm_proc structure so it can be
used for versal where device IDs are used instead of
node IDs.
To accommodate this change header files are re-organized.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
ZynqMP pm_service ipi file uses platform specific macros names.
pm_service ipi functions can be used by other Xilinx platforms
also. Make rename macros to use generic names so that it can be
used by common file.
pm_service ipi functions will be moved to common file in next patch.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Use generic name for pm_api structure member, so that pm_api
structure can be used other Xilinx platforms.
Structure definition will be moved to common file in upcoming
patch.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
ipi_mb functions can be used for other Xilinx platform.
Move it to common file from platform specific files.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
ipi_mb function uses platform specific ipi configuration table.
These ipi_mb functions can be used for other Xilinx platform.
So, instead of using direct data structure, initialize IPI
configuration data by passing platform specific ipi table.
Macros are updated accordingly for this ipi table change.
This change is done so that ipi_mb functions can be moved to
common file without major changes. All common functions now would
be moved to common file in next patch.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Move ipi configuration structure definition to common header file
and rename it to common name, so it can be used for Xilinx specific
other platforms in upcoming changes.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Move zynqmp_ipi.h to platform specific include directory.
Rename it to plat_ipi.h instead of platform name. So, it can
be used to common source files which needs platform specific
data.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Move zynqmp_def.h to platform specific include directory.
Also, update source file to include header file from updated
path of zynqmp_def.h
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Move zynqmp_private.h to platform specific include directory.
Also, rename it to plat_private.h instead of having platform
name. So, it can be used to common source files which needs
platform specific data.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
A previous commit 89f2e58985 ("plat/arm: remove weak implemention of
'plat_arm_psci_override_pm_ops' function") introduced a problem with the
CSS_USE_SCMI_SDS_DRIVER configuration. In juno_pm.c the
css_scmi_override_pm_ops function was used regardless of whether the
flag was set. This patch ifdefs the function to restore the original
behaviour.
Change-Id: I508025ba70cf3a9250cc6270c1df209179c37ae7
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
Update some asserts that refer to #defines that only occur in
ARM platforms, preventing this code to be used on other platforms.
Instead, use a platform agnostic name, and update all the existing
users.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Update the reported Renesas version to 2.0.0, since the DDR/QoS/PFC
table versions match the ones from that release.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Add code to determine the platform timer frequency and configure
the generic timer accordingly early in BL2.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Since the interrupts are handled in EL3, dump the EL3 error registers
in case an error happens.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Add missing TARGET_NAME for the case where RCAR_LSI is set to AUTO,
which is platform auto-detection.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Call the function only from architecture setup and at the end of
suspend cycle instead of calling it all over the place.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to
correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the
hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable
BL2 area.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Staticize the platform memory map tables as they are only used within
the platform_common.c file.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Add missing dependency on the bl2.elf and bl31.elf into the rcar_srecord
target, which uses those ELF files to generate the SRECs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Rename the H3 label to avoid confusing clang, which generates an error
if the label is just H3. Rename it to RCARH3.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This patch removes the dependency of the N1SDP on soc
css defines in order to let the N1SDP platform port
define the uart related constants.
Change-Id: If13796f278586a01512ee99615502b30e478189e
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
The top level makefile defines the PLAT variable, not PLATFORM.
This mistake was causing an empty variable expansion and showing an
incomplete error message.
Change-Id: I5da1275c73c61a7c1823643a76300f255841719d
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
The patch SHA 55cf015c enabled PIE support when RESET_TO_BL31=1 for
all ARM platforms. But it seems n1sdp platform doesn't work with PIE
support yet. Hence restrict the ENABLE_PIE=1 to fvp platform.
Change-Id: If44e42528e4b0b57c69084503f346576fe0748bd
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Instead, only platform_def.h is included.
The required files to be included are added in stm32mp1_def.h.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This clock does not drive any clock in LPD so there is no need for
Linux to try to initialize it.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Linux has no reason to use these system and debug clocks and therefore
shouldn't access them. These clocks are marked as invalid in order to
prevent Linux from registering and querying them.
Note that despite clocks being marked as invalid a security issue
still remains in place as there is nothing that prevents the
non-secure world from gating these clocks and that way causing
damage to the system.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
These clocks are marked as invalid in order to prevent Linux from
registering them.
Note that despite clocks being marked as invalid a security issue
still remains in place as there is nothing that prevents the
non-secure world from gating these clocks and that way halt
the whole APU subsystem.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
In the existing model for ACPU clock the mux, divider, and gate were
represented as one clock and ACPU_HALF was modelled as child of
ACPU clock. This is not correct. ACPU clock model contains only
mux and the divider, and it has 2 children: ACPU_FULL and ACPU_HALF
clocks which have only gates. The models of ACPU and ACPU_HALF clocks
are fixed and ACPU_FULL clock is added.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Clock get parent EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock set parent API to get pre_src, post_src, div2
and bypasss, in the implementation of pm_clock_get_parent() we need to
workaround this by distinguishing two cases:
1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC,
*_POST_SRC, *_INT_MUX or *_PLL clock IDs); or
2) given clock ID is truly an on-chip clock.
For case 1) we'll map the call onto PLL-specific EEMI API with the
respective parameter ID. For case 2) the call is passed to the PMU.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Clock set parent EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock set parent API to set pre_src, post_src, div2
and bypass, in the implementation of pm_clock_set_parent() we need to
workaround this by distinguishing two cases:
1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC,
*_POST_SRC, *_INT_MUX or *PLL clock IDs); or 2) given clock ID is truly
an on-chip clock.
For case 1) we'll map the call onto PLL set parameter EEMI API with the
respective parameter ID. Since clock set parent interface to EL1/2 receives
parent index (mux select value), the value is just passed to PMU.
Functions that appear to be unused after this change is made are removed.
Setting the parent of *PLL clocks, that actually model bypass, is not
possible. This is already ensured by the existing clock model having the
CLK_SET_RATE_NO_REPARENT flag. The API also doesn't allow changing the
bypass parent. Bypass is controlled only by the PMU firmware.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Clock set/get rate are not implemented and will likely never be.
Remove empty function stubs.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Clock get divider EEMI API is reimplemented to use system-level clock
get divider EEMI API rather than direct MMIO read/write accesses to clock
control registers.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Clock set divider EEMI API is reimplemented to use system-level clock
set divider EEMI API rather than direct MMIO read/write accesses to clock
control registers.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Clock get state EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux is_enabled method for PLLs still uses clock get state API
get the PLL state, in the implementation of pm_clock_getstate() we need
to workaround this by distinguishing two cases: 1) if the given clock ID
corresponds to a PLL output clock ID; or 2) given clock ID is truly an
on-chip clock whose state of the gate should be returned.
For case 1) we'll call pm_api_clock_pll_getstate() implemented in
pm_api_clock.h/c. This function will query the PLL state from PMU using
the system-level PLL get mode EEMI API.
For case 2) we'll call the PMU to query the clock gate state using
system-level clock get status EEMI API.
Functions that appear to be unused after this change is made are removed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Clock disable EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock disable API to reset the PLL in the
implementation of pm_clock_disable() we need to workaround this by
distinguishing two cases: 1) if the given clock ID corresponds to a PLL
output clock ID; or 2) given clock ID is truly an on-chip clock that can
be gated.
For case 1) we'll call pm_api_clock_pll_disable() implemented in
pm_api_clock.h/c. This function will reset the PLL using the system-level
PLL set mode EEMI API with the reset mode argument.
For case 2) we'll call the PMU to configure the clock gate. This is done
using system-level clock disable EEMI API.
Functions that appear to be unused after this change is made are removed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Clock enable EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock enable API to trigger locking of the PLLs
in the pm_clock_enable() implementation we need to workaround this by
distinguishing two cases: 1) if the given clock ID corresponds to a PLL
output clock ID; or 2) given clock ID is truly an on-chip clock that can
be gated.
For case 1) we'll call pm_api_clock_pll_enable() implemented in
pm_api_clock.h/c. This function checks what is the buffered PLL mode and
calls the system-level PLL set mode EEMI API with the buffered mode value
specified as argument. Long term, if linux driver get fixed to use PLL
EEMI API to control PLLs, this case could be removed from ATF.
For case 2) we'll call the PMU to configure the clock gate. This is done
using system-level clock enable EEMI API.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
When linux calls pm_ioctl_get_pll_frac_mode() it doesn't expect the actual
mode to be read from hardware, but the value that it is intending to
program. Therefore, we return the buffered value to linux.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
When linux calls pm_ioctl_set_pll_frac_mode() it doesn't expect the
fractional mode to be changed in hardware. Furthermore, even before this
patch setting the mode which is done by writing into register takes
no effect until the PLL reset is deasserted, i.e. until linux "enables"
the PLL. To adjust the code to system-level PLL EEMI API and avoid
unnecessary IPIs that would otherwise be issued, we buffer the mode
value set via IOCTL until the PLL mode really needs to be set.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Fractional data should be set using PLL set parameter EEMI API. This
stands for system-level communication (APU to PMU). Since linux
already uses a specific IOCTL function to do this and we need to
keep it that way, the pll clock ID given by linux has to be mapped
to the pll node ID that is communicated at the system-level (argument
of PLL set parameter API).
With this modification the function pm_api_clk_set_pll_frac_data is
removed from pm_api_clock.c/h because it became unused.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Fractional data should be get using PLL get parameter EEMI API. This
stands for system-level communication (APU to PMU). Since linux
already uses a specific IOCTL function to do this and we need to
keep it that way, the pll clock ID given by linux has to be mapped
to the pll node ID that is communicated at the system-level (argument
of PLL get parameter API).
With this modification the function pm_api_clk_get_pll_frac_data is
removed from pm_api_clock.c/h because it became unused.
The clock enum is defined as 'enum clock_id'.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
This API will be used to get the currently configured PLL mode:
reset (bypassed and unlocked), integer or fractional (locked).
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
This API will be used to set the PLL mode: reset (unlocked), integer
or fractional (locked). If reset mode is set the PM controller will
bypass the target PLL prior to asserting the reset. If integer or
fractional mode is set the PM controller will program and trigger
locking of the PLL. If success status is returned the PLL is locked
and its bypass is deasserted. If fractional mode is set the fractional
divider (data parameter) has to have a non-zero value prior to issuing
pll set fractional mode. The caller need to ensure that the data
parameter is properly set using pll get/set parameter EEMI API.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
This API will be used to get a parameter for the PLL. Parameter values
represent the values as defined in the Zynq MPSoC register reference
manual ug1087.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
This API will be used to set a parameter for the PLL. The parameter
value that is set will have effect once the PLL mode is set to integer
or fractional mode. Parameter values represent the values as defined
in the Zynq MPSoC register reference manual ug1087.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Even though this is not used unless SPD=tspd, only defining it when
SPD_tspd is defined doesn't have any advantage and it makes it harder to
read the code.
Change-Id: I3d93135e05f39be071d16f8a47394a9a3ff54bc8
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This patch converts Tegra platforms to support native
GICv2 drivers. This involves removes Tegra's GIC driver
port platforms to use interrupt_props
Change-Id: I83d8a690ff276dd97928dc60824a4fd36999bb30
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds a macro to allow platforms to compile native
GICv2 drivers along with Tegra handlers.
Change-Id: I8281796c09dae5704cff2daab831395d65e261b7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch allows platforms to define their
own jump table list for library at ROM. The
file has the list of functions to be used
from library at ROM. It can also include
other list files.
Change-Id: I721c35d7dad3dcadbb3a7f3277bfd5d3e1f6e00a
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
As suggested, pass the FDT to BL 33 via x1 instead of x3 , to be
consistent with the other platforms.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
On AARCH32, thumb is used by default, no need to redefine it.
As all our binaries are compiled with thumb, interwork is not needed.
The binaries compiled with or without those flags are the same,
except of course for the date.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
SPM needs to map a number of regions on behalf of the secure partition.
Previously, it used to get a list of them from platform code using the
plat_get_secure_partition_mmap() API. Now it gets them from the resource
description structure.
The SPM<->SP shared buffer is mapped dynamically at EL3. This buffer is
used to pass information between SPM and SP, so it must be mapped at EL3
as well in order to be used by SPM.
Dynamic translation tables have been enabled when the Trusted Firmware
is compiled with SPM support.
Change-Id: I64ad335e931661812a0a60558e60372e1e5e6b72
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Load SP and RD from package instead of relying on RD being already
loaded in memory and the SP being loaded as a BL32 image.
Change-Id: I18d4fbf4597656c6a7e878e1d7c01a8a324f3f8a
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This avoids the following warnings:
no previous prototype for 'bl2_arch_setup' [-Wmissing-prototypes]
no previous prototype for 'plat_log_get_prefix' [-Wmissing-prototypes]
Also correct a compilation issue if BL2_IN_XIP_MEM is enabled:
uintptr_t is not defined.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This information is retrieved from the resource description now.
Change-Id: Iaae23945eb2c45305cdc6442853e42f4e04fe094
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This information is defined by the Secure Partition in the resource
description.
Change-Id: Ia7db90c5de8360a596106880d3f6a632a88d3ea8
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Introduce helpers to create resource description struct, as well as code
to load the information from DTB files.
Change-Id: I0f5bb94eb8b01c6cb53fe807a9db0c05a70d7a43
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This patch makes the build system link the console framework code by
default, like it already does with other common libraries (e.g. cache
helpers). This should not make a difference in practice since TF is
linked with --gc-sections, so the linker will garbage collect all
functions and data that are not referenced by any other code. Thus, if a
platform doesn't want to include console code for size reasons and
doesn't make any references to console functions, the code will not be
included in the final binary.
To avoid compatibility issues with older platform ports, only make this
change for the MULTI_CONSOLE_API.
Change-Id: I153a9dbe680d57aadb860d1c829759ba701130d3
Signed-off-by: Julius Werner <jwerner@chromium.org>
Crash reporting via the default consoles registered by MULTI_CONSOLE_API
has been broken since commit d35cc34 (Console: Use callee-saved
registers), which was introduced to allow console drivers written in C.
It's not really possible with the current crash reporting framework to
support console drivers in C, however we should make sure that the
existing assembly drivers that do support crash reporting continue to
work through the MULTI_CONSOLE_API.
This patch fixes the problem by creating custom console_putc() and
console_flush() implementations for the crash reporting case that do not
use the stack. Platforms that want to use this feature will have to link
plat/common/aarch64/crash_console_helpers.S explicitly.
Also update the documentation to better reflect the new reality (of this
being an option rather than the expected default for most platforms).
Change-Id: Id0c761e5e2fddaf25c277bc7b8ab603946ca73cb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Commit e74afb652 (Deprecate weak crash console functions) deprecated the
default inclusion of weak definitions for plat_crash_console functions
in plat/common/aarch64/platform_helpers.S. The code was later copied out
to plat/common/aarch64/crash_console_helpers.S so platforms can link it
explicitly if they want to. However, since deprecation does not mean
removal, the same code is also still duplicated in platform_helpers.S.
The duplicated code contains both empty stubs for the !MULTI_CONSOLE_API
case, and a real implementation that used to work but was broken by
commit d35cc34 (Console: Use callee-saved registers) for
MULTI_CONSOLE_API. It's not great to have both of these duplicated in
two files, so this patch splits them up: in platform_helpers.S we'll
only keep the empty stubs (guarded by !ERROR_DEPRECATED), which should
not regress functionality since the MULTI_CONSOLE_API implementation was
already broken anyway. In crash_console_helpers.S, we'll only keep the
MULTI_CONSOLE_API version, which is enough both as an implementation in
itself and as a sample for how to reimplement these functions in a
platform-specific file.
Change-Id: I83d95a90ab6aac597dc2ea2f2797ac2c8ed075d4
Signed-off-by: Julius Werner <jwerner@chromium.org>
SGI-Clark.Helios platform is similar to SGI-Clark.Ares platform.
The difference between these two platforms is the CPU type and
the number of CPUs. Add the base support for SGI-Clark.Helios platform.
Change-Id: I2b04cb3fb953907848b4fab016e3648899ca4256
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
For SGI-Clark.Helios platform, at present, only the CPU power ON/OFF
ops are supported. So override the PSCI ops to allow callbacks only
for CPU power ON/OFF operations.
Change-Id: Idc0a3deb78cb850310cbe849d77604fa9881579c
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
SGI-Clark.Helios platform is based on multi-threaded CPUs and uses an
additional thread power domain level as well.
Define a power domain tree descriptor 'sgi_clark_helios_pd_tree_desc'
for SGI-Clark.Helios platform and let the function
'plat_get_power_domain_tree_desc' pick up the correct power
domain tree descriptor based on the platform.
Change-Id: Ibc6d551b570bc740053316a3608c455679d9155b
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Generate a /reserved-memory node for FCNL in the DT passed to
subsequent stages, so they will know how the FCNL is configured.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Generate /compatible string for the platform, so that the subsequent
stages know which platform they are running on. This could be useful
when ie. building U-Boot that contains DTs for multiple platforms and
can thus decide on which platform it is running. This would ultimately
allow single bootloader binary for all Gen3 platforms.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Pass DTB containing DRAM layout from BL2 to BL33 via register x3, so
that the BL33 can simply consume it and get accurate DRAM layout info.
BL33 is in most usecases U-Boot.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Use array of start-size tuples for the DRAM banks and call single
function which iterates over this array to report the DRAM info.
This is in preparation for expanding this to generate FDT for the
next stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Print the DRAM configuration only after the DRAM was initialized. This
will be useful when deduplicating code populating FDT passed to U-Boot,
since it will contain the same macros as bl2_advertise_dram_size().
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Bryan O'Donoghue
Anson Huang
Antonio Niño Díaz
Igor Opaniuk
Anthony Zhou
Sam Payne
Harvey Hsieh
Krishna Reddy
Varun Wadekar
Marvin Hsu
Soby Mathew
Ard Biesheuvel
Paul Beesley
Joel Hutton
Jolly Shah
Marek Vasut
Deepak Pandey
Sandrine Bailleux
Yann Gautier
Sathees Balya
Julius Werner
Chandni Cherukuri