Commit Graph

5634 Commits

Author SHA1 Message Date
Julius Werner d9af1f7b6f Add helper to parse BL31 parameters (both versions)
BL31 used to take a single bl31_params_t parameter structure with entry
point information in arg0. In commit 726002263 (Add new version of image
loading.) this API was changed to a more flexible linked list approach,
and the old parameter structure was copied into all platforms that still
used the old format. This duplicated code unnecessarily among all these
platforms.

This patch adds a helper function that platforms can optionally link to
outsource the task of interpreting arg0. Many platforms are just
interested in the BL32 and BL33 entry point information anyway. Since
some platforms still need to support the old version 1 parameters, the
helper will support both formats when ERROR_DEPRECATED == 0. This allows
those platforms to drop a bunch of boilerplate code and asynchronously
update their BL2 implementation to the newer format.

Change-Id: I9e6475adb1a7d4bccea666118bd1c54962e9fc38
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-07-23 20:25:34 -07:00
Julius Werner 57bf605772 Factor out cross-BL API into export headers suitable for 3rd party code
This patch adds a new include/export/ directory meant for inclusion in
third-party code. This is useful for cases where third-party code needs
to interact with TF-A interfaces and data structures (such as a custom
BL2-implementation like coreboot handing off to BL31). Directly
including headers from the TF-A repository avoids having to duplicate
all these definitions (and risk them going stale), but with the current
header structure this is not possible because handoff API definitions
are too deeply intertwined with other TF code/headers and chain-include
other headers that will not be available in the other environment.

The new approach aims to solve this by separating only the parts that
are really needed into these special headers that are self-contained and
will not chain-include other (non-export) headers. TF-A code should
never include them directly but should instead always include the
respective wrapper header, which will include the required prerequisites
(like <stdint.h>) before including the export header. Third-party code
can include the export headers via its own wrappers that make sure the
necessary definitions are available in whatever way that environment can
provide them.

Change-Id: Ifd769320ba51371439a8e5dd5b79c2516c3b43ab
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-07-23 20:25:34 -07:00
Julius Werner 9352be8803 Use explicit-width data types in AAPCS parameter structs
It's not a good idea to use u_register_t for the members of
aapcs64_params_t and aapcs32_params_t, since the width of that type
always depends on the current execution environment. This would cause
problems if e.g. we used this structure to set up the entry point of an
AArch32 program from within an AArch64 program. (It doesn't seem like
any code is doing that today, but it's probably still a good idea to
write this defensively. Also, it helps with my next patch.)

Change-Id: I12c04a85611f2b6702589f3362bea3e6a7c9f776
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-07-23 20:25:34 -07:00
Julius Werner c1185ffde1 plat/rockchip: Switch to use new common BL aux parameter library
This patch changes all Rockchip platforms to use the new common BL aux
parameter helpers. Since the parameter space is now cleanly split in
generic and vendor-specific parameters and the COREBOOT_TABLE
parameter is now generic, the parameter type number for that parameter
has to change. Since it only affects coreboot which always builds TF as
a submodule and includes its headers directly to get these constants,
this should not cause any issues. In general, after this point, we
should avoid changing already assigned parameter type numbers whenever
possible.

Change-Id: Ic99ddd1e91ff5e5fe212fa30c793a0b8394c9dad
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-07-23 20:25:30 -07:00
Julius Werner b852d229f3 Introduce lightweight BL platform parameter library
This patch adds some common helper code to support a lightweight
platform parameter passing framework between BLs that has already been
used on Rockchip platforms but is more widely useful to others as well.
It can be used as an implementation for the SoC firmware configuration
file mentioned in the docs, and is primarily intended for platforms
that only require a handful of values to be passed and want to get by
without a libfdt dependency. Parameters are stored in a linked list and
the parameter space is split in generic and vendor-specific parameter
types. Generic types will be handled by this code whereas
vendor-specific types have to be handled by a vendor-specific handler
function that gets passed in.

Change-Id: If3413d44e86b99d417294ce8d33eb2fc77a6183f
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-07-18 16:42:40 -07:00
Soby Mathew d0d0f17164 Merge changes from topic "jc/shift-overflow" into integration
* changes:
  Enable -Wshift-overflow=2 to check for undefined shift behavior
  Update base code to not rely on undefined overflow behaviour
  Update hisilicon drivers to not rely on undefined overflow behaviour
  Update synopsys drivers to not rely on undefined overflow behaviour
  Update imx platform to not rely on undefined overflow behaviour
  Update mediatek platform to not rely on undefined overflow behaviour
  Update layerscape platform to not rely on undefined overflow behaviour
  Update intel platform to not rely on undefined overflow behaviour
  Update rockchip platform to not rely on undefined overflow behaviour
  Update renesas platform to not rely on undefined overflow behaviour
  Update meson platform to not rely on undefined overflow behaviour
  Update marvell platform to not rely on undefined overflow behaviour
2019-07-16 10:11:27 +00:00
Soby Mathew dc150425c3 Merge "synquacer: Fix compilation fail for SPM support build config" into integration 2019-07-15 15:01:11 +00:00
Madhukar Pappireddy 91e6bef9f5 synquacer: Fix compilation fail for SPM support build config
Fix the header file path

Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I73a92a3f0049ecbda7eade452405927c04048e01
2019-07-12 09:12:11 -05:00
Sandrine Bailleux 9b35070249 Merge changes I94acd1bb,I0ece5226,I82d0a213,Ia4fc9456,Ic9fb7ed1 into integration
* changes:
  rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.4
  rcar_gen3: drivers: rpc: Modify PFC code
  rcar_gen3: drivers: rpc: Change RPC PHY calibration setting
  rcar_gen3: drivers: ddr-b: Update DDR setting for H3, M3, M3N
  rcar_gen3: drivers: ddr-a: Update E3 DDR setting
2019-07-12 12:00:08 +00:00
Sandrine Bailleux 3ce3ce0738 Merge "Re-apply GIT_COMMIT_ID check for checkpatch" into integration 2019-07-12 11:26:04 +00:00
Toshiyuki Ogasahara 363fb55a91 rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.4
Update the revision number in the revision management file.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I94acd1bb53d9d2453e550e2a13b6391b9088ff8d
2019-07-12 12:11:38 +02:00
Toshiyuki Ogasahara c186ec5139 rcar_gen3: drivers: rpc: Modify PFC code
Modify PFC code and rename macro of MFIS according to Errata of
Hardware User's Manual

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I0ece522647319286350843bbbe8b8ba8b0ae9bac
2019-07-12 12:11:38 +02:00
Toshiyuki Ogasahara a3aa877c9e rcar_gen3: drivers: rpc: Change RPC PHY calibration setting
Modify RPC code according to Errata of Hardware User's Manual

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I82d0a2136c7f18870842f84c49343977708eef1e
2019-07-12 12:11:38 +02:00
Chiaki Fujii 783c5304b2 rcar_gen3: drivers: ddr-b: Update DDR setting for H3, M3, M3N
[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.36.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ia4fc9456876a14a9cf3ced93163477974f6cc8bf
2019-07-12 12:11:37 +02:00
John Tsichritzis cf57ff8b99 Re-apply GIT_COMMIT_ID check for checkpatch
As it turns out, Gerrit's merge commits don't always respect that format
so these mistakes have to be ignored as false positives.

Change-Id: I4e38d9c34c95588e7916fba4c154f017d8c92dec
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-07-12 11:06:24 +01:00
Sandrine Bailleux 70f7c4e121 Merge "AArch64: Add 128-bit integer types definitions" into integration 2019-07-12 08:37:24 +00:00
Justin Chadwell 93c690eba8 Enable -Wshift-overflow=2 to check for undefined shift behavior
The -Wshift-overflow=2 option enables checks for left bit shifts.
Specifically, the option will warn when the result of a shift will be
placed into a signed integer and overflow the sign bit there, which
results in undefined behavior.

To avoid the warnings from these checks, the left operand of a shift can
be made an unsigned integer by using the U() macro or appending the u
suffix.

Change-Id: I50c67bedab86a9fdb6c87cfdc3e784f01a22d560
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-12 09:12:19 +01:00
Justin Chadwell 3e43121ed1 Update base code to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: Iddd6f38139a4c6e500468b4fc48d04e0939f574e
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-12 09:12:19 +01:00
Justin Chadwell d3b6df7c3b Update hisilicon drivers to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: I67984b6c48c08af61e95a4dbd18047e2c3151f9a
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-12 09:12:19 +01:00
Justin Chadwell 9264f0876e Update synopsys drivers to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: I54560fe290e7dc52d364d0fe1c81a16f4c8d9a7b
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-12 09:12:19 +01:00
Justin Chadwell dc5baeb3c2 Update imx platform to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: Ia0a10b4a30e63c0cbf1d0f8dfe5768e0a93ae1c7
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-12 09:12:19 +01:00
Justin Chadwell 621d5f2a5b Update mediatek platform to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: If5a88e1b880bcb2be2278398cf5109a6d877e632
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-12 09:12:12 +01:00
Sandrine Bailleux b53cde7920 Merge "Remove references to old project name from common files" into integration 2019-07-12 07:37:36 +00:00
Sandrine Bailleux 2d78a1c6a3 Merge "Fix RST rendering problem" into integration 2019-07-12 07:35:28 +00:00
Hiroyuki Nakano 4b5c1f3060 rcar_gen3: drivers: ddr-a: Update E3 DDR setting
[IPL/DDR]
- Update E3 DDR setting rev.0.12.

Signed-off-by: Hiroyuki Nakano <hiroyuki.nakano.cj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ic9fb7ed1cd7588fab169a99c4070a8dfc40038dc
2019-07-12 06:38:10 +02:00
John Tsichritzis 274e8714ed Merge "Aarch64: Fix SCTLR bit definitions" into integration 2019-07-11 15:39:02 +00:00
John Tsichritzis ec92cbcb6a Merge "plat/intel: Fix SMPLSEL for MMC" into integration 2019-07-11 12:37:26 +00:00
John Tsichritzis f15d7e8325 Merge "driver: synopsys: emmc: Do not change FIFO TH as this breaks some platforms" into integration 2019-07-11 12:28:15 +00:00
Justin Chadwell 9e4afb0272 Update layerscape platform to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: Ib63ef6e2e4616dd56828bfd3800d5fe2df109934
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-11 12:10:58 +01:00
Justin Chadwell 36cfbf3ca2 Update intel platform to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: I4c7a315cb18b3bbe623e7a7a998d2dac869638a7
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-11 12:10:58 +01:00
Justin Chadwell 79ca7807cc Update rockchip platform to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: Ib7fc54e4141cc4f1952a18241bc18671b36e2168
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-11 12:10:58 +01:00
Justin Chadwell 673406b508 Update renesas platform to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: I51278beacbe6da79853c3f0f0f94cd806fc9652c
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-11 12:10:58 +01:00
Justin Chadwell 1578169edd Update meson platform to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: Ib7ec8ed3423e9b9b32be2388520bc27ee28f6370
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-11 12:10:58 +01:00
Justin Chadwell b19498b97b Update marvell platform to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: I78f386f5ac171d6e52383a3e42003e6fb3e96b57
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-11 12:10:51 +01:00
Tien Hock, Loh 9ce41ec59b driver: synopsys: emmc: Do not change FIFO TH as this breaks some platforms
Designware MMC DMA FIFO threshold shouldn't be changed as it broke
Poplar platform's uboot MMC

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I87ec9d5a78e1bf45119cb73797e402b25a914c13
2019-07-11 09:55:31 +00:00
John Tsichritzis b10fae86d9 Merge "Rename Cortex-Deimos to Cortex-A77" into integration 2019-07-11 09:12:40 +00:00
Alexei Fedorov 394fa5d499 AArch64: Add 128-bit integer types definitions
This patch adds 128-bit integer types int128_t and uint128_t
for "__int128" and "unsigned __int128" supported by GCC and
Clang for AArch64.

Change-Id: I0e646d026a5c12a09fd2c71dc502082052256a94
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-07-10 12:22:58 +01:00
Alexei Fedorov c465515718 Aarch64: Fix SCTLR bit definitions
This patch removes incorrect SCTLR_V_BIT definition and adds
definitions for ARMv8.3-Pauth EnIB, EnDA and EnDB bits.

Change-Id: I1384c0a01f56f3d945833464a827036252c75c2e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-07-10 11:26:45 +01:00
Balint Dobszay f363deb6d4 Rename Cortex-Deimos to Cortex-A77
Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
2019-07-10 12:14:20 +02:00
John Tsichritzis bd97f83a62 Remove references to old project name from common files
The project has been renamed from "Arm Trusted Firmware (ATF)" to
"Trusted Firmware-A (TF-A)" long ago. A few references to the old
project name that still remained in various places have now been
removed.

This change doesn't affect any platform files. Any "ATF" references
inside platform files, still remain.

Change-Id: Id97895faa5b1845e851d4d50f5750de7a55bf99e
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-07-10 11:13:00 +01:00
Tien Hock, Loh 0943ea379f plat/intel: Fix SMPLSEL for MMC
MMC sample select needs to be set properly so that DWMMC clock can be
driven to 50Mhz

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a
2019-07-10 11:39:03 +08:00
John Tsichritzis 9f0a0bbd1c Fix RST rendering problem
Change-Id: Ic5aab23b549d0bf8e0f7053b46fd59243214aac1
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-07-09 18:09:03 +01:00
Sandrine Bailleux 21bde92ff6 Merge "plat: imx8m: Add caam module init on imx8m" into integration 2019-07-09 12:33:31 +00:00
Sandrine Bailleux a83d8d2ced Merge changes from topic "jts/reword" into integration
* changes:
  docs: removing references to GitHub
  Change checkpatch.conf after migration to tf.org
2019-07-09 12:24:28 +00:00
Sandrine Bailleux 2cbeee4d51 Merge "rpi3: Fix compilation error when stack protector is enabled" into integration 2019-07-08 16:21:01 +00:00
Madhukar Pappireddy f6de960fb7 rpi3: Fix compilation error when stack protector is enabled
Include necessary header file to use ARRAY_SIZE() macro

Change-Id: I5b7caccd02c14c598b7944cf4f347606c1e7a8e7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2019-07-08 10:45:48 -05:00
John Tsichritzis d012c012e8 docs: removing references to GitHub
Change-Id: Ibdee91ad337ee362872924d93e82f5b5e47e63d9
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-07-08 12:52:33 +01:00
John Tsichritzis 65b5a4b993 Change checkpatch.conf after migration to tf.org
A specific checkpatch setting was used because of GitHub. This necessity
doesn't exist anymore.

Change-Id: Ie2225a5cb88654f3b7407e43e0a48fafa9a9165c
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-07-08 12:47:48 +01:00
Sandrine Bailleux 996d379309 Merge "tools/fiptool: Add Makefile.msvc to build on Windows." into integration 2019-07-05 11:25:17 +00:00
Sandrine Bailleux ef4b8d5a80 Merge "uniphier: support console based on multi-console" into integration 2019-07-05 11:22:09 +00:00