Commit Graph

1828 Commits

Author SHA1 Message Date
John Tsichritzis 7cdb43470a Support shared Mbed TLS heap for SGI
Change-Id: Iac454c745543842bfeed004aee7a3f4fb94d37e1
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-09-04 10:33:08 +01:00
John Tsichritzis ba597da7fd Support shared Mbed TLS heap for FVP
This patch introduces the shared Mbed TLS heap optimisation for Arm
platforms. The objective is the Mbed TLS heap to be shared between BL1
and BL2 so as to not allocate the heap memory twice. To achieve that,
the patch introduces all the necessary helpers for implementing this
optimisation. It also applies it for FVP.

Change-Id: I6d85eaa1361517b7490956b2ac50f5fa0d0bb008
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-09-04 10:32:22 +01:00
John Tsichritzis 6d01a46334 Prepare Mbed TLS drivers for shared heap
The Mbed TLS drivers, in order to work, need a heap for internal usage.
This heap, instead of being directly referenced by the drivers, now it
is being accessed indirectly through a pointer. Also, the heap, instead
of being part of the drivers, now it is being received through the
plat_get_mbedtls_heap() function. This function requests a heap from the
current BL image which utilises the Mbed TLS drivers.

Those changes create the opportunity for the Mbed TLS heap to be shared
among different images, thus saving memory. A default heap
implementation is provided but it can be overridden by a platform
specific, optimised implemenetation.

Change-Id: I286a1f10097a9cdcbcd312201eea576c18d157fa
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-09-04 10:32:06 +01:00
Soby Mathew ebf417aa83
Merge pull request #1540 from MISL-EBU-System-SW/marvell-updates-18.09
Marvell updates 18.09
2018-09-04 03:35:54 +01:00
Konstantin Porotchkin 586714901a plat: marvell: Update Marvell base code version to 18.09.1
Change-Id: I908844364bf8080612aaa6d750d7d2441ecc2eb8
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-09-03 16:06:18 +03:00
Christine Gharzuzi 1ab4df76bf plat: svc: ap807: add SVC configuration for AP807
- add svc configuration according to values burnt
  to the chip efuse

Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03 16:06:11 +03:00
Konstantin Porotchkin dd47809e9e fix: marvell: Check the required libraries before building doimage
Some customers are missing host libraries required for doimage
builds.
This patch requests for the library installation check for every
doimage build and suggest the required installation steps in case
of missing headers.

Change-Id: Icde18c3d4d6045f65e50d2dc9e6514971f40033e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
2018-09-03 16:05:54 +03:00
Marcin Wojtas fd1718a2ff plat: a8k: enable PMU overflow interrupt handler
This patch enables handling PMU overflow IRQ by GIC SPI's
directly in EL3. Also implement additional SMC routine,
which can disable the solution on demand in runtime.

Since it is possible to configure PMU interrupt trigger type
in the MADT ACPI table, it is enough to set it only once in EL3
during initialization.

Change-Id: Ie76aa62ccc4fd7cabfec9e3d5ed9970ada1c1b2a
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03 15:47:09 +03:00
Soby Mathew d853d3b2de
Merge pull request #1541 from rajanv-xilinx/integration-num-clocks
zynqmp: pm: Add API to get number of clocks
2018-09-03 08:56:19 +01:00
Marcin Wojtas 155d01ff1e marvell: pm: do not panic by default in cpu_standby
Current default behavior of cpu_standby callback
is problematic during the SBSA test, which is
unable to run due to EL3 panic. Make it dependent on
the PM firmware running.

Change-Id: I7a53de8c880bd23b157dd65ce14bb48b5a5c76c8
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-02 14:10:47 +03:00
Marcin Wojtas b0f2361a1a plat: marvell: a80x0: reconfigure CP0 PCIE0 windows
In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SATA/USB cards, reconfigure the I/O windows so we can declare two
MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64
one at 0x8_0000_0000. In addition, this will leave ample room for an
ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB)

For compatibility with older kernels or firmware, leave the original
16 MB window in place as well.

Change-Id: Ia8177194e542078772f90941eced81b231c16887
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-02 14:10:47 +03:00
Marcin Wojtas 5b0a152a57 plat: marvell: a70x0: reconfigure CP0 PCIE2 windows
In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SATA/USB cards, reconfigure the I/O windows so we can declare two
MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64
one at 0x8_0000_0000. In addition, this will leave ample room for an
ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB)

For compatibility with older kernels or firmware, leave the original
16 MB window in place as well.

Change-Id: I80b00691ae8d0a3f3f7285b8e0bfc21c0a095e94
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-02 14:10:47 +03:00
Grzegorz Jaszczyk de5cba28c4 a8k: use the memory controller feature to protect the RT service region
Define the RT service space as secure with use of memory controller
trustzone feature. Thanks to this protection, any NS-Bootloader nor NS-OS,
won't be able to access RT services (e.g. accidentally overwrite it,
which will at best result in RT services unavailability).

Change-Id: Ie5b6cbe9a1b77879d6d8f8eac5d4e41e468496ce
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-02 14:10:47 +03:00
Konstantin Porotchkin 94d6dd677b plat: marvell: rename common include file
Rename a8k_common.h to armada_common.h to keep the same header
name across all other Marvell Armada platforms.
This is especially useful since various Marvell platforms may
use common platform files and share the driver modules.

Change-Id: I7262105201123d54ccddef9aad4097518f1e38ef
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-09-02 14:10:47 +03:00
Andrew F. Davis 34cae37f58 ti: k3: common: Add basic PSCI core off support
Use TI-SCI messages to request core power down from system controller
firmware.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-08-31 09:23:21 -05:00
Dimitris Papastamos 5acb793288
Merge pull request #1550 from danielboulby-arm/db/weakdefs
Prevent two weak definitions of the same function
2018-08-31 13:18:18 +01:00
Daniel Boulby 490eeb04e6 Prevent two weak definitions of the same function
Add another level of abstraction of weak defs for
arm_bl2_handle_post_image_load to prevent two weak definitions
of the same function

Change-Id: Ie953786f43b0f88257c82956ffaa5fe0d19603db
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-08-30 17:50:55 +01:00
Antonio Nino Diaz 5a22e461b5 Fix MISRA defects in log helpers
No functional changes.

Change-Id: I850f08718abb69d5d58856b0e3de036266d8c2f4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-30 16:22:52 +01:00
Dimitris Papastamos dcf95e7e90
Merge pull request #1542 from antonio-nino-diaz-arm/an/bl31-misra
Some MISRA fixes in BL31, cci and smmu
2018-08-30 16:18:49 +01:00
Dimitris Papastamos 612fa95006
Merge pull request #1539 from antonio-nino-diaz-arm/an/gic-misra
MISRA fixes for the GIC driver
2018-08-30 16:08:25 +01:00
Antonio Nino Diaz c9512bca3b Fix MISRA defects in BL31 common code
Change-Id: I5993b425445ee794e6d2a792c244c0af53640655
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-30 09:22:33 +01:00
Antonio Nino Diaz e0ced7a9fb plat/common: gic: MISRA fixes
Change-Id: I11509a3271d7608048d49e7dd5192be0c2a313f0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-30 09:22:16 +01:00
Soby Mathew a542faadde
Merge pull request #1514 from glneo/for-upstream-psci
K3 PSCI Support
2018-08-30 05:37:13 +01:00
Dimitris Papastamos a23b3db5e9
Merge pull request #1538 from jts-arm/typos
Remove unnecessary casts
2018-08-28 10:07:21 +01:00
Dimitris Papastamos 3c065eb1d2
Merge pull request #1531 from MISL-EBU-System-SW/marvell-plat-updates
plat: marvell: bl31: Update the early platform setup API
2018-08-28 10:06:00 +01:00
Rajan Vaja ec9712cee1 zynqmp: pm: Add API to get number of clocks
Currently in Linux maximum number of clocks is hard-coded and
so it needs to allocate static memory. It can get actual clock
number after querying all clock names by special clock name
string. Add new query data parameter to get actual number of
clocks so Linux can get actual clock numbers in advance.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
2018-08-27 06:49:46 -07:00
John Tsichritzis 432f0ad0bb Remove unnecessary casts
Small patch which removes some redundant casts to (void *).

Change-Id: If1cfd68f2989bac1d39dbb3d1c31d4119badbc21
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-08-23 12:57:35 +01:00
Andrew F. Davis c8761b4dbb ti: k3: common: Add basic PSCI reset support
Use TI-SCI messages to request reset from system controller firmware.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-08-22 10:57:19 -05:00
Andrew F. Davis df83b0348b ti: k3: common: Add basic PSCI core on support
Use TI-SCI messages to request core start from system controller
firmware.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-08-22 10:57:19 -05:00
Andrew F. Davis 89ea53c705 ti: k3: drivers: ti_sci: Add support for Processor control
TI-SCI message protocol provides support for controlling of various
physical cores available in the SoC. In order to control which host is
capable of controlling a physical processor core, there is a processor
access control list that needs to be populated as part of the board
configuration data.

Introduce support for the set of TI-SCI message protocol APIs that
provide us with this capability of controlling physical cores.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
2018-08-22 10:57:19 -05:00
Andrew F. Davis 7b8f3e2db3 ti: k3: drivers: ti_sci: Add support for Core control
Since system controller now has control over SoC power management, core
operation such as reset need to be explicitly requested to reboot the SoC.
Add support for this here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
2018-08-22 10:57:19 -05:00
Andrew F. Davis 6d1dfef6bf ti: k3: drivers: ti_sci: Add support for Clock control
TI-SCI message protocol provides support for management of various
hardware entities within the SoC.

In general, we expect to function at a device level of abstraction,
however, for proper operation of hardware blocks, many clocks directly
supplying the hardware block needs to be queried or configured.

Introduce support for the set of TI-SCI message protocol support that
provide us with this capability.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
2018-08-22 10:57:19 -05:00
Andrew F. Davis 3858452d31 ti: k3: drivers: ti_sci: Add support for Device control
TI-SCI message protocol provides support for management of various
hardware entitites within the SoC.

We introduce the fundamental device management capability support to
the driver protocol as part of this change.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
2018-08-22 10:57:17 -05:00
Andrew F. Davis b5c2e1c42c ti: k3: drivers: Add support for TI System Control Interface protocol
Texas Instrument's System Control Interface (TI-SCI) Message Protocol
is used in Texas Instrument's System on Chip (SoC) such as those
in K3 family AM654x SoCs to communicate between various compute
processors with a central system controller entity.

TI-SCI message protocol provides support for management of various
hardware entities within the SoC. Add support driver to allow
communication with system controller entity within the SoC.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
2018-08-22 10:56:32 -05:00
Andrew F. Davis d76fdd33e0 ti: k3: drivers: Add Secure Proxy driver
Secure Proxy module manages hardware threads that are meant
for communication between the processor entities. Add support
for this here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-08-22 10:33:09 -05:00
Antonio Nino Diaz 39b6cc66d6 libc: Use printf and snprintf across codebase
tf_printf and tf_snprintf are now called printf and snprintf, so the
code needs to be updated.

Change-Id: Iffeee97afcd6328c4c2d30830d4923b964682d71
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-22 10:26:05 +01:00
Antonio Nino Diaz 93c78ed231 libc: Fix all includes in codebase
The codebase was using non-standard headers. It is needed to replace
them by the correct ones so that we can use the new libc headers.

Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-22 10:26:05 +01:00
Dimitris Papastamos 11dfe0b49a
Merge pull request #1532 from jeenu-arm/misra-fixes
MISRA fixes
2018-08-22 10:25:41 +01:00
Dimitris Papastamos 36d4707441
Merge pull request #1530 from antonio-nino-diaz-arm/an/rpi3-deprecated
rpi3: Migrate from deprecated APIs
2018-08-22 10:24:06 +01:00
Roberto Vargas 9d57a147b8 memprotect: Move files to specific platform makefiles
All the arm platforms were including the files related to
mem-protect. This configuration generates some problems
with new platforms that don't support such functionality,
and for that reason this patch moves these files to the
platform specific makefiles.

Change-Id: I6923e5224668b76667795d8e11723cede7979b1e
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-08-21 12:48:48 +01:00
Dimitris Papastamos 4c0b164e64
Merge pull request #1524 from danielboulby-arm/db/ReclaimInit
rockchip: Add plat_is_my_cpu_primary function
2018-08-20 09:38:17 +01:00
Jeenu Viswambharan b634fa910e SiP: MISRA fixes for execution state switch
These changes address most of the required MISRA rules. In the process,
some from generic code is also fixed.

No functional changes.

Change-Id: I707dbec9b34b802397e99da2f5ae738165d6feba
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-08-20 09:05:39 +01:00
Konstantin Porotchkin bbaa712ee9 plat: marvell: bl31: Update the early platform setup API
Move from bl31_early_platform_setup to bl31_early_platform_setup2

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-08-19 10:11:24 +03:00
Antonio Nino Diaz 941a624dbc rpi3: Migrate from deprecated APIs
Change-Id: If53b5b2430a06ce8cf6e7948765b560b37afc335
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-17 14:25:08 +01:00
Dimitris Papastamos 4e45fbd626
Merge pull request #1525 from antonio-nino-diaz-arm/an/rpi3
rpi3: Remove dependencies on Arm platform code
2018-08-17 09:55:38 +01:00
Antonio Nino Diaz 42636360ac rpi3: Remove dependencies on Arm platform code
The Raspberry Pi 3 port doesn't actually depend on any Arm platform
code, so the dependencies can be removed.

Change-Id: Ic2f47f5001bebde3862815b1d880a169d82b3f65
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-15 14:43:29 +01:00
Daniel Boulby 5eddd22e05 rockchip: Add plat_is_my_cpu_primary function
This function is required for platforms where
COLD_BOOT_SINGLE_CPU=0 however it was missing from rockchip
platforms

Change-Id: I32a85f226a4f22085a27113903f34bdb6f28dbcc
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-08-15 13:39:33 +01:00
Dimitris Papastamos 07da0bf976
Merge pull request #1516 from antonio-nino-diaz-arm/an/printf
Replace stdio.h functions by TF functions
2018-08-15 10:49:57 +01:00
Dimitris Papastamos 3ba9295715
Merge pull request #1510 from robertovargas-arm/romlib
Add support for moving libraries to ROM
2018-08-13 13:02:16 +01:00
Dimitris Papastamos 0983b8b149
Merge pull request #1519 from antonio-nino-diaz-arm/an/xlat-el2
xlat v2: Support EL2 translation regime
2018-08-13 13:02:04 +01:00
Antonio Nino Diaz 4c72c3fefa layerscape: stm32mp1: Migrate to enable_mmu_svc_mon()
Change-Id: I3d16b247a0fa457e6293e2d2c4503dfde1e51c1d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-10 13:47:37 +01:00
Antonio Nino Diaz 1e54cbb8f5 plat/arm: Migrate to enable_mmu_svc_mon()
Change-Id: I1bb310e1b05968d30b28913c4011c0601e1ae64e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-10 13:47:37 +01:00
Antonio Nino Diaz 1a92a0e00a xlat v2: Support the EL2 translation regime
The translation library is useful elsewhere. Even though this repository
doesn't exercise the EL2 support of the library, it is better to have it
here as well to make it easier to maintain.

enable_mmu_secure() and enable_mmu_direct() have been deprecated. The
functions are still present, but they are behind ERROR_DEPRECATED and
they call the new functions enable_mmu_svc_mon() and
enable_mmu_direct_svc_mon().

Change-Id: I13ad10cd048d9cc2d55e0fff9a5133671b67dcba
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-10 13:47:11 +01:00
Haojian Zhuang eba1b6b3c7 plat/poplar: migrate to mmc framework
Migrate from emmc framework to mmc framework.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2018-08-10 17:11:12 +08:00
Haojian Zhuang 261e43b78f plat/hikey: migrate to mmc framework
Migrate to mmc framework.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2018-08-10 17:11:12 +08:00
Antonio Nino Diaz 6a23356c4f Replace stdio.h functions by TF functions
Functions provided by stdio.h such as printf and sprintf are available
in the codebase, but they add a lot of code to the final image if they
are used:

- AArch64: ~4KB
- AArch32: ~2KB in T32, ~3KB in A32

tf_printf and tf_snprintf are a lot more simple, but it is preferable
to use them when possible because they are also used in common code.

Change-Id: Id09fd2b486198fe3d79276e2c27931595b7ba60e
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-10 09:36:18 +01:00
Roberto Vargas 1eb735d753 Add librom support in FVP
Change-Id: Idb9ba3864d6de3053260724f07172fd32c1523e0
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-08-06 13:08:51 +01:00
Nariman Poushin 354596f683 plat/arm: Add support for SGM775
Add support for System Guidance for Mobile platform SGM775

Change-Id: I2442a50caae8f597e5e5949cd48f695cf75d9653
Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
2018-08-03 17:42:54 +01:00
Deepak Pandey 5b2a7813a8 css_pm_scmi: optimise cpu suspend to remove redundant scmi call
In css platforms where the cpu/cluster management is done by the hardware,
software does need to issue certain scmi requests.

This patch wraps those scmi calls around the HW_ASSISTED_COHERENCY
build option to remove them on platforms that have this hardware support.

Change-Id: Ie818e234484ef18549aa7f977aef5c3f0fc26c27
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
2018-08-03 17:42:54 +01:00
Nariman Poushin eb5e1be431 plat/arm: tzc_dmc500: Add missing plat_arm.h include
This omission causes a build error as the definition for
arm_tzc_regions_info_t is needed from plat_arm.h

Change-Id: I26935ee90d3e36ab6a016ff2c4eee4413df3e4e8
Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
2018-08-03 17:42:54 +01:00
Nariman Poushin 58192800e0 plat/arm: css: Set MT bit in incoming mpidr arugments
Change-Id: I278d6876508800abff7aa2480910306a24de5378
Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
2018-08-03 17:42:53 +01:00
Chandni Cherukuri a41d1b2ce3 plat/sgi: switch to using scmi
The Arm SGI platforms can switch to using SCMI. So enable support for
SCMI and remove portions of code that would be unused after switching
to SCMI.

Change-Id: Ifd9e1c944745f703da5f970b5daf1be2b07ed14e
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
2018-08-03 16:17:33 +05:30
Chandni Cherukuri 8e1cc44900 sgi: disable CPU power down bit in reset handler
On SGI platforms, the 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1'
register requires an explicit write to clear it for hotplug and
idle to function correctly. The reset value of this bit is zero
but it still requires this explicit clear to zero. This indicates
that this could be a model related issue but for now this issue can
be fixed be clearing the CORE_PWRDN_EN in the platform specific
reset handler function.

Change-Id: I4222930daa9a3abacdace6b7c3f4a5472ac0cb19
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
2018-08-03 16:17:33 +05:30
Roberto Vargas fec3648478 Create a library file for libfdt
TF Makefile was linking all the objects files generated for the
fdt library instead of creating a static library that could be
used in the linking stage.

Change-Id: If3705bba188ec39e1fbf2322a7f2a9a941e1b90d
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-08-03 11:31:26 +01:00
Dimitris Papastamos f68bc8a1c2
Merge pull request #1506 from danielboulby-arm/db/SeparateCodeAndROData
Fix build for SEPARATE_CODE_AND_RODATA=0
2018-08-03 10:56:47 +01:00
Daniel Boulby 2ecaafd2e8 Fix build for SEPARATE_CODE_AND_RODATA=0
TF won't build since no memory region is specified
for when SEPARATE_CODE_AND_RODATA=0 it still relies on
the ARM_MAP_BL_RO_DATA region which is never defined for
this case. Create memory region combining code and RO data for
when the build flag SEPARATE_CODE_AND_RODATA=0 to fix this

Change-Id: I6c129eb0833497710cce55e76b8908ce03e0a638
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-08-01 16:26:26 +01:00
Dimitris Papastamos 72bc63185c
Merge pull request #1498 from glneo/cache-early-fixes
Early cache enable and coherency fixes
2018-07-30 16:53:34 +01:00
Dimitris Papastamos 2ee596c498
Merge pull request #1493 from antonio-nino-diaz-arm/an/xlat-misra
Fix MISRA defects in xlat tables lib and SP805 driver
2018-07-30 16:44:43 +01:00
Antonio Nino Diaz e7b9886c7c xlat: Fix MISRA defects
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.

Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-30 09:30:15 +01:00
Soby Mathew eef90a772d
Merge pull request #1497 from SNG-ARM/master
RAS changes for SGI575 platform
2018-07-27 11:03:13 +01:00
Soby Mathew 128dad9a20
Merge pull request #1494 from hzhuang1/pcie_pin
Hikey960: configure pins for PCIe controller
2018-07-27 11:02:36 +01:00
Kaihua Zhong 16bec9c25b Hikey960: configure pins for PCIe controller
GPIO_089 connects to PCIE_PERST_N. It needs to be configured as
output low.

Signed-off-by: Kaihua Zhong <zhongkaihua@huawei.com>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2018-07-27 16:24:23 +08:00
Andrew F. Davis 903f13d312 ti: k3: common: Only enable caches early
We can enter and exit coherency without any software operations,
but HW_ASSISTED_COHERENCY has stronger implications that are
causing issues. Until these can be resolved, only use the weaker
WARMBOOT_ENABLE_DCACHE_EARLY flag.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-07-26 14:31:06 -05:00
Sughosh Ganu f29d18289a RAS: SGI: Add flags needed to build components for RAS feature
Add the various flags that are required to build the components needed
to enable the RAS feature on SGI575 platform. By default, all flags
are set to 0, disabling building of all corresponding components.

Change-Id: I7f8536fba895043ef6e397cc33ac9126cb572132
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
2018-07-26 22:13:44 +05:30
Sughosh Ganu 167dae4dc6 RAS: SGI575: Add platform specific RAS changes
Add platform specific changes needed to add support for the RAS
feature on SGI575 platform, including adding a mapping for the
CPER buffer being used on SGI575 platform.

Change-Id: I01a982e283609b5c48661307906346fa2738a43b
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
2018-07-26 22:10:27 +05:30
Sughosh Ganu 485fc95443 RAS: SGI: Add platform handler for RAS interrupts
Add a platform specific handler for RAS interrupts and configure the
platform RAS interrupts for EL3 handling. The interrupt handler passes
control to StandaloneMM code executing in S-EL0, which populates the
CPER buffer with relevant error information. The handler subsequently
invokes the SDEI client which processes the information in the error
information in the CPER buffer. The helper functions
plat_sgi_get_ras_ev_map and plat_sgi_get_ras_ev_map_size would be
defined for sgi platforms in the subsequent patch, which adds sgi575
specific RAS changes.

Change-Id: I490f16c15d9917ac40bdc0441659b92380108d63
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
2018-07-26 22:03:32 +05:30
Sughosh Ganu d952391914 SPM: SGI: Map memory allocated for secure partitions
The secure partition manager reserves chunks of memory which are used
for the S-EL0 StandaloneMM image and the buffers required for
communication between the Non-Secure world with the StandaloneMM
image. Add the memory chunks to relevant arrays for mapping the
regions of memory with corresponding attributes.

Change-Id: If371d1afee0a50ca7cacd55e16aeaca949d5062b
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
2018-07-26 22:02:39 +05:30
Sughosh Ganu 2e4a509dde ARM platforms: Allow board specific definition of SP stack base
The SGI platforms need to allocate memory for CPER buffers. These
platform buffers would be placed between the shared reserved memory
and the per cpu stack memory, thus the need to redefine stack base
pointer for these platforms. This patch allows each board in ARM
platform to define the PLAT_SP_IMAGE_STACK_BASE.

Change-Id: Ib5465448b860ab7ab0f645f7cb278a67acce7be9
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
2018-07-26 22:01:29 +05:30
Sughosh Ganu d9cc9372e1 SGI: Include arm_spm_def.h in platform_def.h
Include arm_spm_def.h in the platform_def.h file. Without this
inclusion, we get build errors like

In file included from services/std_svc/spm/sp_setup.c:12:0:
services/std_svc/spm/sp_setup.c: In function 'spm_sp_setup':
services/std_svc/spm/sp_setup.c:61:57: error: 'PLAT_SPM_BUF_BASE'
  undeclared (first use in this function)
  write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, PLAT_SPM_BUF_BASE);

Now that the platform_def.h includes arm_spm_def.h, remove inclusion
of platform_def.h in arm_spm_def.h to remove the circular dependency.

Change-Id: I5225c8ca33fd8d288849524395e436c3d56daf17
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
2018-07-26 22:00:26 +05:30
Sughosh Ganu 46b69e3de1 Include board_arm_def.h through the platform's header
The board_arm_def.h header file needs to be included via the platform
definition header. Not doing so, results in a redefinition error of
PLAT_ARM_MAX_BL31_SIZE macro, if defined in the platform definition
file.

Change-Id: I1d178f6e8a6a41461e7fbcab9f6813a2faa2d82b
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
2018-07-26 21:52:38 +05:30
danh-arm 60e062fb0e
Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra
Fix several MISRA defects in PSCI library
2018-07-25 16:09:54 +01:00
danh-arm d87d524ee4
Merge pull request #1466 from Yann-lms/stm32mp1
Add STMicroelectronics STM32MP1 platform support
2018-07-25 16:05:35 +01:00
danh-arm cad25f1484
Merge pull request #1491 from jeenu-arm/misra-fix
Arm platforms: Fix type mismatch for arm_pm_idle_states
2018-07-25 15:23:25 +01:00
danh-arm f94523ed9e
Merge pull request #1472 from danielboulby-arm/db/Reclaim
Rework page table setup for varying number of mem regions
2018-07-25 15:16:24 +01:00
Yann Gautier f74cbc93a8 stm32mp1: Link BL2, BL32 and DTB in one binary
platform.mk is updated to have compilation rules for DTB, stm32image tool,
and the concatenation of the 3 binaries.
A new linker script and an assembly file are added to manage this.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2018-07-24 17:18:41 +02:00
Yann Gautier 964dfee1a2 stm32mp1: Add BL32 SP_min secure monitor
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2018-07-24 17:18:32 +02:00
Yann Gautier 10a511ceaa stm32mp1: Add DDR support and its security with TZC400
The DDR driver is under dual license, BSD and GPLv2.
The configuration parameters are taken from device tree.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2018-07-24 17:18:19 +02:00
Yann Gautier e4f559ff54 stm32mp1: Add PMIC support
If a PMIC companion chip is present on board, it has to be configured
for regulators supplies.
This check is done with board DT configuration.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>
2018-07-24 17:15:13 +02:00
Yann Gautier 278c34df06 stm32mp1: Add console support
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2018-07-24 17:14:39 +02:00
Yann Gautier e58a53fb72 stm32mp1: save boot information in backup registers
This will be used by BL33 to get boot device and instance.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2018-07-24 17:14:22 +02:00
Yann Gautier 6a339a4952 stm32mp1: Add GPIO support
The management of pinctrl nodes of device tree is also added.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2018-07-24 17:14:08 +02:00
Yann Gautier 7839a05090 stm32mp1: Add clock and reset support
The clock driver is under dual license, BSD and GPLv2.
The clock driver uses device tree, so a minimal support for this is added.
The required files for driver and DTS files are in include/dt-bindings/.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2018-07-24 17:13:36 +02:00
Yann Gautier 4353bb20cc Introduce STMicroelectronics STM32MP1 platform
STM32MP1 is a microprocessor designed by STMicroelectronics,
based on a dual Arm Cortex-A7.
It is an Armv7-A platform, using dedicated code from TF-A.

STM32MP1 uses BL2 compiled with BL2_AT_EL3.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>
2018-07-24 17:11:43 +02:00
Daniel Boulby d323af9e3d Rework page table setup for varying number of mem regions
Change arm_setup_page_tables() to take a variable number of memory
regions. Remove coherent memory region from BL1, BL2 and BL2U as
their coherent memory region doesn't contain anything and
therefore has a size of 0. Add check to ensure this
doesn't change without us knowing.

Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-07-24 15:01:57 +01:00
danh-arm cffb003428
Merge pull request #1488 from b49020/integration
synquacer: Enable optional OP-TEE support
2018-07-24 14:37:23 +01:00
danh-arm 790e6c5b96
Merge pull request #1485 from jeenu-arm/ras
Double-fault and fatal error handling support
2018-07-24 14:36:43 +01:00
Sumit Garg 6cb2a39703 synquacer: Enable optional OP-TEE support
OP-TEE loading is optional on Developerbox controlled via SCP
firmware. To check if OP-TEE is loaded or not, we use DRAM1 region
info passed by SCP firmware.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
2018-07-24 17:12:22 +05:30
Jeenu Viswambharan ecd62429af Arm platforms: Fix type mismatch for arm_pm_idle_states
This also gets rid of MISRA violations for Rule 8.3 and 8.4.

Change-Id: I45bba011b16f90953dd4b260fcd58381f978eedc
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-07-24 10:28:50 +01:00
Antonio Nino Diaz 2bc3dba924 PSCI: Fix MISRA defects in platform code
Fix violations of MISRA C-2012 Rules 10.1, 10.3, 13.3, 14.4, 17.7 and
17.8.

Change-Id: I6c9725e428b5752f1d80684ec29cb6c52a5c0c2d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-24 09:12:16 +01:00
Haojian Zhuang 99eb5ae86d hikey: include TBB in BL1
BL1 is used in recovery mode on HiKey. The TBB implementation
on HiKey is in BL2. It means that user need to build ATF BL2
with TBB and ATF BL1 with non-TBB. It's inconvenient.

So include TBB in BL1, too.

Signed-off-by: Teddy Reed <teddy@prosauce.org>
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2018-07-22 09:35:44 +08:00
Antonio Nino Diaz 1083b2b315 PSCI: Fix types of definitions
Also change header guards to fix defects of MISRA C-2012 Rule 21.1.

Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-20 13:49:22 +01:00
danh-arm ba0248b52d
Merge pull request #1450 from MISL-EBU-System-SW/marvell-support-v6
Marvell support for Armada 8K SoC family
2018-07-19 17:11:32 +01:00
danh-arm 992a353613
Merge pull request #1483 from antonio-nino-diaz-arm/an/rpi3-psci
rpi3: PSCI and Linux boot improvements
2018-07-19 15:37:54 +01:00
danh-arm e4686fd860
Merge pull request #1449 from theopolis/hikey-tbb
hikey: Add experimental TBB support
2018-07-19 11:49:56 +01:00
danh-arm 8ff0dfa79c
Merge pull request #1482 from sandrine-bailleux-arm/sb/fix-hcptr
Misc arch.h fixes and cleanup
2018-07-19 11:36:58 +01:00
Jeenu Viswambharan eaeaa4d048 RAS: Introduce handler for EL3 EAs
External Aborts while executing in EL3 is fatal in nature. This patch
allows for the platform to define a handler for External Aborts received
while executing in EL3. A default implementation is added which falls
back to platform unhandled exception.

Change-Id: I466f2c8113a33870f2c7d2d8f2bf20437d9fd354
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-07-19 10:13:18 +01:00
Jeenu Viswambharan d5a23af50f RAS: Introduce handler for Double Faults
Double fault is when the PE receives another error whilst one is being
handled. To detect double fault condition, a per-CPU flag is introduced
to track the status of error handling. The flag is checked/modified
while temporarily masking external aborts on the PE.

This patch routes double faults to a separate platform-defined handler.

Change-Id: I70e9b7ba4c817273c55a0af978d9755ff32cc702
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-07-19 10:13:18 +01:00
Jeenu Viswambharan b56dc2a98c RAS: Introduce handler for Uncontainable errors
Uncontainable errors are the most severe form of errors, which typically
mean that the system state can't be trusted any more. This further means
that normal error recovery process can't be followed, and an orderly
shutdown of the system is often desirable.

This patch allows for the platform to define a handler for Uncontainable
errors received. Due to the nature of Uncontainable error, the handler
is expected to initiate an orderly shutdown of the system, and therefore
is not expected to return. A default implementation is added which falls
back to platform unhandled exception.

Also fix ras_arch.h header guards.

Change-Id: I072e336a391a0b382e77e627eb9e40729d488b55
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-07-19 10:13:17 +01:00
Konstantin Porotchkin 34ec7ec310 plat: marvell: Add board support for A8K platform
Add support for A8K platform boards

Change-Id: Ife025d930d2ab6cabbc13bbe19b2273cc1c938c8
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin 486f868bab plat: marvell: Add common ARMADA platform components
Add common Marvell ARMADA platform components.
This patch also includes common components for Marvell
ARMADA 8K platforms.

Change-Id: I42192fdc6525a42e46b3ac2ad63c83db9bcbfeaf
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Soby Mathew 2e4eea1b11
Merge pull request #1471 from Anson-Huang/master
Add i.MX8QX/i.MX8QM power management feature
2018-07-18 13:35:29 +01:00
Antonio Nino Diaz 30399885f5 Fix types of arch.h definitions
Define the values as unsigned int or unsigned long long based on the
actual size of the register. This prevents subtle issues caused by
having a type that is too small. For example:

    #define OPTION_ENABLE 0x3
    #define OPTION_SHIFT  32

    uint64_t mask = OPTION_ENABLE << OPTION_SHIFT;

Because OPTION_ENABLE fits in an int, the value is considered an int.
This means that, after shifting it 32 places to the left, the final
result is 0. The correct way to define the values is:

    #define OPTION_ENABLE ULL(0x3)
    #define OPTION_SHIFT  U(32)

In this case, the compiler is forced to use a 64 bit value from the
start, so shifting it 32 places to the left results in the expected
value.

Change-Id: Ieaf2ffc2d8caa48c622db011f2aef549e713e019
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-18 11:09:54 +01:00
Soby Mathew 344e40379c
Merge pull request #1480 from sandrine-bailleux-arm/topics/sb/debug-macros
Always compile debug macros
2018-07-18 10:48:03 +01:00
Antonio Nino Diaz aa49bde8a3 rpi3: Move NS-DRAM out of the protected region
The Non-secure DRAM region shouldn't be protected in the range specified
in the Linux command line with memmap.

This change also increases the size of the Secure DRAM region.

Change-Id: I306e9e443a84b834c99739f54a534a3ca3be2424
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Antonio Nino Diaz 76c944a48d rpi3: Add support for direct Linux kernel boot
This option allows the Trusted Firmware to pass the correct arguments to
a 32 or 64-bit Linux kernel without the need of an intermediate loader
such as U-Boot.

Change-Id: I2b22e8933fad6a614588ace559f893e97329801f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Antonio Nino Diaz 6d924ca91b rpi3: Don't wire mailbox 3 to FIQ line
FIQs shouldn't be used at all as long as the interrupt routing doesn't
support them properly.

Change-Id: Ib1db7b523a62de2035d41197bc791048337cf791
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Antonio Nino Diaz 6297d6feb0 rpi3: Fix warm entrypoint setup for PSCI_CPU_ON
Remove unused variable and set the secure entrypoint correctly.

Change-Id: I7447ea62771092de6be35704077ae28c519d6993
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Antonio Nino Diaz 1aad932ce6 rpi3: Add support for the stack protector
It uses the hardware RNG in a similar way as Juno (it gets 128 bits of
entropy and does xor on them).

It is disabled by default.

Change-Id: I8b3adb61f5a5623716e0e8b6799404c68dd94c60
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Antonio Nino Diaz 4ad2696d88 rpi3: Introduce hardware RNG driver
Note that this is a non-secure RNG. This is only useful for educational
purposes.

Change-Id: If359c8d0f755ef8e416986de7fbca34679a523e1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Antonio Nino Diaz 98967fb14a rpi3: Remove broken support of RESET_TO_BL31
There is no way to boot BL31 at the addresses specified in the platform
memory map unless an extra loader is used at address 0x00000000. It is
better to remove it to prevent confusion. Having it enabled was a bug.

Change-Id: I3229fbc080f5996cff47efce8e799bae94e0d5cb
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Soby Mathew f9d2808a1c
Merge pull request #1478 from antonio-nino-diaz-arm/an/rpi3-improvements
rpi3: A few improvements
2018-07-16 14:22:10 +01:00
Antonio Nino Diaz 4f2f66a280 rpi3: Detect board revision
Implement VideoCore mailbox interface driver and use it to get the board
revision identifier.

For now it is only used to print the model for debug purposes.

This wiki contains the documentation of the mailbox interface:

https://github.com/raspberrypi/firmware/wiki

Change-Id: I11943b99b52cc1409f4a195ebe58eb44ae5b1d6c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-14 02:15:55 +01:00
Antonio Nino Diaz 42ba8f747b rpi3: Implement PSCI_SYSTEM_OFF
This implementation doesn't actually turn the system off, it simply
reboots it and prevents it from booting while keeping it in a low power
mode.

Change-Id: I7f72c9f43f25ba0341db052bc2be4774c88a7ea3
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-14 02:15:51 +01:00
Antonio Nino Diaz 64fe343c03 rpi3: Concatenate BL1 and FIP automatically
Add a new default makefile target to concatenate BL1 and the FIP and
generate armstub8.bin. This way it isn't needed to do it manually.

Documentation updated to reflect the changes.

Change-Id: Id5b5b1b7b9f87767db63fd01180ddfea855a7207
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-13 15:27:01 +01:00
Dimitris Papastamos 9ceda8b907
Merge pull request #1477 from dp-arm/dp/css-ap-core
CSS: Add support for SCMI AP core config protocol
2018-07-13 15:23:29 +01:00
Sandrine Bailleux c426fd709f Tegra: Fix up INFO() message
With commit cf24229e6e ("Run compiler on debug macros for type
checking"), the compiler will now always evaluate INFO() macro
calls, no matter the LOG_LEVEL value. Therefore, any variable
referenced in the macro has to be be defined.

Address this issue by removing the local variable and using the
expression it was assigned directly in the INFO() call.

Change-Id: Iedc23b3538c1e162372e85390881e50718e50bf3
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-07-13 11:31:17 +02:00
Dimitris Papastamos 6e779ace0a
Merge pull request #1476 from grandpaul/paulliu-rpi3-modify-size
rpi3: enlarge SEC_DRAM0_SIZE for optee_test to pass
2018-07-12 11:53:37 +01:00
Dimitris Papastamos 1be2f666dd
Merge pull request #1464 from antonio-nino-diaz-arm/an/rpi3-ints
rpi3: Implement simple interrupt routing
2018-07-12 11:52:53 +01:00
Dimitris Papastamos 2a246d2e32 CSS: Use SCMI AP core protocol to set the warm boot entrypoint
Change-Id: Iaebbeac1a1d6fbd531e5694b95ed068b7a193e62
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-07-12 10:09:12 +01:00
Dimitris Papastamos bfe3c449a7 Add support for SCMI AP core configuration protocol v1.0
Change-Id: If07000b6b19011e960336a305a784dd643301b97
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-07-12 10:09:12 +01:00
Anson Huang 8ef9f860c0 imx: imx8qm: add domain suspend/resume support
Add domain suspend/resume support, Linux kernel
can "echo mem > /sys/power/state" to put system
into suspend mode, all CPUs and cluster will be
powered off and can be waked up if irq pending
in GIC, tested on i.MX8QM MEK board.

Since the power state has been implemented, switch
to use standard power state for CCI operations
instead of private cpu use count in i.MX8QM.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-12 16:16:55 +08:00
Anson Huang 0f53bca05c imx: imx8qm: add domain off support
Add domain off support for Linux kernel's cpu
hot-plug feature, when there are cpu off request
from Linux kernel, TF-A will send command to
system controller to do CPU power gate accordingly,
tested on i.MX8QM MEK board.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-12 16:15:56 +08:00
Anson Huang d31ffcf0f7 imx: imx8qm: add system reset support
Add system reset support for i.MX8QM,
when Linux kernel issues "reboot" command,
TF-A will send command to inform system
controller to reset whole board according
to board design, tested on i.MX8QM MEK board.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-12 16:15:51 +08:00
Anson Huang db81c59252 imx: imx8qm: add system off support
Add system power off support for i.MX8QM,
when Linux kernel issues "poweroff" command,
TF-A will send command to inform system
controller to power off whole board according
to board design, tested on i.MX8QM MEK board.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-12 16:15:39 +08:00
Anson Huang 762688bff2 imx: imx8qx: add domain suspend/resume support
Add domain suspend/resume support, Linux kernel
can "echo mem > /sys/power/state" to put system
into suspend mode, all CPUs and cluster will be
powered off and can be waked up if irq pending
in GIC, tested on i.MX8QX MEK board.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-12 16:15:32 +08:00
Ying-Chun Liu (PaulLiu) 8ebf806fc5 rpi3: enlarge SEC_DRAM0_SIZE for optee_test to pass
Running optee_test failed because SEC_DRAM0_SIZE is too small. Previous
is 2 MB. We enlarge it to 11 MB for passing the test. Also we reduce
the NS_DRAM0_SIZE from 13MB to 4MB so that the whole section is still
fit in 16MB.

This commit also modified the document to reflect the changes we've
made in code.

Tested-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
2018-07-12 13:51:35 +08:00
Anson Huang 3260f5c7c8 imx: imx8qx: add domain off support
Add domain off support for Linux kernel's cpu
hot-plug feature, when there are cpu off request
from Linux kernel, TF-A will send command to
system controller to do CPU power gate accordingly.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-12 11:12:39 +08:00
Anson Huang 351e3731ca imx: imx8qx: add system reset support
Add system reset support for i.MX8QX,
when Linux kernel issues "reboot" command,
TF-A will send command to inform system
controller to reset whole board according
to board design, tested on i.MX8QX MEK board.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-12 11:05:21 +08:00
Anson Huang 8972694e93 imx: imx8qx: add system off support
Add system power off support for i.MX8QX,
when Linux kernel issues "poweroff" command,
TF-A will send command to inform system
controller to power off whole board according
to board design, tested on i.MX8QX MEK board.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-12 11:00:41 +08:00
Antonio Nino Diaz d35de55e55 rpi3: Implement simple interrupt routing
Implement minimal interrupt routing functions. All interrupts are
treated as non-secure interrupts to be handled by the non-secure world.

Add note to the documentation about disabling FIQs qhen using OP-TEE
with Linux.

Change-Id: I937096542d973925e43ae946c5d0b306d0d95a94
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-11 21:00:32 +01:00
Sandrine Bailleux ed8c3743ef ARM platforms: Remove some duplicate declarations
The plat_arm_mmap variable is already declared in plat_arm.h, which is
included from plat/arm/common/arm_common.c.

Similarly, plat_arm.h declares the 'plat_arm_psci_pm_ops' variable, which
does not need to be declared again in plat/arm/common/arm_pm.c.

The duplication was not compliant with MISRA rule 8.5.

Change-Id: Icc42547cc025023226b1078a7ec4f06d093364b7
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-07-11 17:33:29 +02:00
Sandrine Bailleux 6c77e74915 Fix some violations to MISRA rule 8.3
Wherever we use 'struct foo' and 'foo_t' interchangeably in a
function's declaration and definition, use 'struct foo' consistently
for both, as per the TF-A coding guidelines [1].

[1] https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Coding-Guidelines#avoid-anonymous-typedefs-of-structsenums-in-header-files

Change-Id: I7998eb24a26746e87e9b6425529926406745b721
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-07-11 17:33:29 +02:00
Joel Hutton c84b6cb1aa Add initial CPU support for Cortex-Deimos
Change-Id: I2c4b06423fcd96af9351b88a5e2818059f981f1b
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-07-11 13:26:48 +01:00
Dimitris Papastamos 6cbf17d114
Merge pull request #1473 from robertovargas-arm/misra
Misra
2018-07-11 13:15:52 +01:00
Roberto Vargas b2805dabaa Remove .func and .endfunc assembler directives
These directives are only used when stabs debugging information
is used, but we use ELF which uses DWARF debugging information.
Clang assembler doesn't support these directives, and removing
them makes the code more compatible with clang.

Change-Id: I2803f22ebd24c0fe248e04ef1b17de9cec5f89c4
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-07-11 09:22:56 +01:00
Roberto Vargas 5629b2b11c Use ALIGN instead of NEXT in linker scripts
Clang linker doesn't support NEXT. As we are not using the MEMORY command
to define discontinuous memory for the output file in any of the linker
scripts, ALIGN and NEXT are equivalent.

Change-Id: I867ffb9c9a76d4e81c9ca7998280b2edf10efea0
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-07-11 09:21:02 +01:00
Roberto Vargas 311a1a8ee8 Fix MISRA rule 8.4
Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined

Fixed for:
	make DEBUG=1 PLAT=juno SPD=tspd CSS_USE_SCMI_SDS_DRIVER=1 all

Change-Id: Id732c8df12ef3e20903c41b7ab9a9b55341d68ac
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-07-10 13:54:48 +01:00
Roberto Vargas 0fbb7a4afe Fix MISRA rule 8.3
Rule 8.3: All declarations of an object or function shall
              use the same names and type qualifiers.

Fixed for:
make DEBUG=1 PLAT=juno SPD=tspd CSS_USE_SCMI_SDS_DRIVER=1 all

Change-Id: Id9dcc6238b39fac6046abc28141e3ef5e7aa998d
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-07-10 13:33:05 +01:00
Roberto Vargas a9b5b4aea1 Fix MISRA rule 8.4
Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined

Fixed for:
	make DEBUG=1 PLAT=juno ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32

Change-Id: I3ac25096b55774689112ae37bdf1222f9a9ecffb
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-07-10 11:17:53 +01:00
Roberto Vargas c96f297f8d Fix MISRA rule 8.3
Rule 8.3: All declarations of an object or function shall
              use the same names and type qualifiers.

Fixed for:
	make DEBUG=1 PLAT=juno ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32

Change-Id: Ia34f5155e1cdb67161191f69e8d1248cbaa39e1a
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-07-10 11:17:51 +01:00