Pull out mailbox driver into common area as they can be shared between
intel's socfpga platform
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716
Share socfpga private definitions and storage driver between Agilex and
Stratix 10 platform.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.
Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
Add the UART3 base definition for serial output, which is used on some
PX30 SoM boards.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Change-Id: I8490b15c9f129a33c01cb78bd78675014bc7b015
CPU0 is default on, so it doesn't need to run pwr_domain_on() at
boot. CPU0 AARCH64 will be set in pwr_domain_suspend(), but it may
encounter race condition with other CPUs.
Now AARCH64 will be set with cluster on in pwr_domain_on(), and
all CPUs on this cluster will be set together. It doesn't need to
set AARCH64 again in pwr_domain_suspend(), so the race condition
can be avoided.
Change-Id: I5693ad56e4901f82badb0fc0d8d13e4c9acfe648
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Implement rdist save/resore functions to support low power scenarios.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I9ddc077a04f843275fbe2e868cdd0bd00d622de7
-Wlogical-op prevents common errors with using numerical constants where
a boolean one is expected as well as when the operands of a logical
operator are the same. While these are perfectly valid behavior, they
can be a sign that something is slightly off.
This patch adds this warning to gcc and it's closest equivalent to
clang, while also fixing any warnings that enabling them causes.
Change-Id: Iabadfc1e6ee0c44eef6685a23b0aed8abef8ce89
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Variable shadowing is, according to the C standard, permitted and valid
behaviour. However, allowing a local variable to take the same name as a
global one can cause confusion and can make refactoring and bug hunting
more difficult.
This patch moves -Wshadow from WARNING2 into the general warning group
so it is always used. It also fixes all warnings that this introduces
by simply renaming the local variable to a new name
Change-Id: I6b71bdce6580c6e58b5e0b41e4704ab0aa38576e
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
* changes:
Tegra194: remove L2 ECC parity protection setting
Tegra194: sip_calls: mark unused parameter as const
Tegra194: implement handler to retrieve power domain tree
Tegra194: mce: fix function declaration conflicts
Tegra194: add macros to read GPU reset status
Tegra194: skip notifying MCE in fake system suspend
Tegra194: Enable system suspend
ROMLIB extract functions code from BL images to put them inside ROM.
This has for effect to reduce the size of the BL images.
This patch take this size reduction into consideration to optimize the
memory layout of BL2.
A new "PLAT_ARM_BL2_ROMLIB_OPTIMIZATION" macro is defined and used to
reduce "PLAT_ARM_MAX_BL2_SIZE". This allows to remove the gap between
BL1 and BL2 when ROMLIB is used and provides more room for BL31.
The current memory gain is 0x6000 for fvp and 0x8000 for juno.
Change-Id: I71c2c2c63b57bce5b22a125efaefc486ff3e87be
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
And return NULL if we didn't get them in bl aux params otherwise reset and poweroff
will be broken on platforms that do not have reset and poweroff GPIOs.
Fixes: c1185ffde1 ("plat/rockchip: Switch to use new common BL aux parameter library")
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Change-Id: Ic6cf6383d8f05d745e2c5d5e1b1df38514ea8429
The number of levels in the topology has not changed but the count of
processing elements on the lowest layer is now multiplied by the value
of FVP_MAX_PE_PER_CPU.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: Ia1568a40ea33dbbbcdfab6c8ab6d19f4db0b8eb4
This patch removes the code to enable L2 ECC parity protection
bit, as Tegra194 does not have any Cortex-A57 CPUs.
Change-Id: I4b56595fea2652e8bb8ab4a7ae7567278ecff9af
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
This patch marks the unused parameter 'cookie', to the
plat_sip_handler() function, as const to fix an issue
flagged by the MISRA scan.
Change-Id: I53fdd2caadf43fef17fbc3a50a18bf7fdbd42d39
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch implements the platform handler to return the pointer
to the power domain tree.
Change-Id: I74ea7002c7a461a028b4a252bbd354256fdc0647
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
To fix MISRA defects, remove union in t186 MCE drivers
this driver should compatible with that.
Change-Id: I09e96a1874dd86626c7e41c92a1484a84e387402
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
This patch adds macros to check the GPU reset status bit, before
resizing the VideoMem region.
Change-Id: I4377c1ce1ac6d3bd14c7db83526b99d72bdb41ed
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
- In pre-silicon platforms, MCE might not be ready
to support system suspend(SC7)
- Thus, in fake system suspend mode, bypass waiting for
MCE's acknowledgment to enter system suspend
Change-Id: Ia3c010ce080c4283ab1233ba82e3e577adca34f6
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
This patch does the following:
1. Populate the cstate info corresponding to system suspend
and communicate it to the MCE
2. Ask for MCE's acknowledgement for entering system suspend
and instruct MCE to get inside system suspend once
permitted
Change-Id: I51e1910e24a7e61e36ac2d12ce271290e433e506
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
* changes:
Tegra194: add macros for security carveout configuration registers
Tegra194: add 'TEGRA_TMRUS_SIZE' macro
Tegra194: Fix TEGRA186_SMMU_CTX_SIZE
Tegra194: Dont run MCE firmware on Emulation
Tegra194: remove GPU, MPCORE and PTC registers from streamid list
Tegra194: Support SMC64 encoding for MCE calls
Tegra194: Enable MCE driver
Tegra194: enable SMMU
Tegra194: add support for multiple SMMU devices
Tegra194: add SMMU and mc_sid support
Tegra194: psci: support for 64-bit TZDRAM base
Tegra194: base commit for the platform
Revert "Tegra: Add support for fake system suspend"
N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link, for now only dual-chip
is supported.
Whether or not multiple chips are present is dynamically probed by
SCP firmware and passed on to TF-A, routing table will be set up
only if multiple chips are present.
Initialize GIC-600 multichip operation by overriding the default GICR
frames with array of GICR frames and setting the chip 0 as routing
table owner.
Change-Id: Ida35672be4bbf4c517469a5b330548d75e593ff2
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Earlier PIE support was enabled for all arm platforms when
RESET_TO_BL31=1, but later on it was restricted only to FVP with patch
SHA d4580d17 because of n1sdp platform.
Now it has been verified that PIE does work for n1sdp platform also, so
enabling it again for all arm platforms.
Change-Id: I05ad4f1775ef72e7cb578ec9245cde3fbce971a5
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
1. Switch ARMPLL_LL/CCIPLL/MAINPLL/MPLL control to SPM
2. Switch CLKSQ1/TDCLKSQ control to SPM
3. Switch ck_off/axi_26m control to SPM
BUG=b:136980838
TEST=system suspend/resume passed
Change-Id: I5c8506f7cf16d5cdaeb5ef8caa60a2992a361e18
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
ARM platform can have a non-contiguous GICR frames. For instance, a
multi socket platform can have two or more GIC Redistributor frames
which are 4TB apart. Hence it is necessary for the `gicv3_rdistif_probe`
function to probe all the GICR frames available in the platform.
Introduce `plat_arm_override_gicr_frames` function which platforms can
use to override the default gicr_frames which holds the GICR base
address of the primary cpu.
Change-Id: I1f537b0d871a679cb256092944737f2e55ab866e
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link for now only dual-chip is
supported.
A single instance of TF-A runs on master chip which should be aware of
slave chip's CPU and memory topology.
This patch updates platform macros to include remote chip's information
and also ensures that a single version of firmware works for both single
and dual-chip setup.
Change-Id: I75799fd46dc10527aa99585226099d836c21da70
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Platform information structure holds information about platform's DDR
size(local/remote) which will be used to zero out the memory before
enabling the ECC capability as well as information about multichip
setup. Multichip and remote DDR information can only be probed in SCP,
SDS region will be used by TF-A to get this information at boot up.
This patch introduces a new SDS to store platform information, which is
populated dynamically by SCP Firmware.previously used mem_info SDS is
also made part of this structure itself.
The platform information is also passed to BL33 by copying it to Non-
Secure SRAM.
Change-Id: I4781dc6a7232c3c0a3219b164d943ce9e3e469ee
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Running TF-A from non-standard location such as DRAM is useful for some
SRAM heavy use-cases. Allow the TF-A binary to be executed from an
arbitrary memory location.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Icd97926e4d97f37d7cde4a92758a52f57d569111
This patch adds macros defining the generalised security carveout
registers. These macros help us program the TZRAM carveout access
and the Video Protect Clear carveout access.
Change-Id: I8f7b24b653fdb702fb57a4097801cb3eae050294
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch defines the macro for the TEGRA_TMRUS aperture size.
Change-Id: I33fb674c6a7be8d02971667e7bf8650b7adc62ef
Signed-off-by: Steven Kao <skao@nvidia.com>
TEGRA186_SMMU_CTX_SIZE should match the numbe of elements
in smmu_ctx_regs, which is defined in smmu_plat_config.h.
The current number of elements are 0x490.
Change-Id: If0614ea8ef8b6a8f5da1a3279abaf9255eb76420
Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
Dont run MCE firmware on pre-silicon emulation platforms
Change-Id: I2a8d653e46f494621580ca92271a18e62f648859
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
GPU, MPCORE and PTC clients are changed and not going through SMMU.
Removing it from streamid list.
Change-Id: I14b450a11f02ad6c1a97e67e487d6d624911d019
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
This patch uses SMC64 encoding for all MCE SMC calls originating
from the linux kernel.
Change-Id: Ic4633de5c638566012db033bbaf8c9d9343acdc0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch enable MCE driver for T19x SoC. The MCE driver
takes care of the communication with the MCE firmware to
achieve:
- Cold boot
- Warm boot
- Core/Cluster/System Power management
- Custom MCE requests
Change-Id: I75854c0b649a691e9b244d9ed9fc1c19743e3e8d
Signed-off-by: Steven Kao <skao@nvidia.com>
This patch adds support for all three SMMU devices present on the SoC.
The following changes have been done:
Add SMMU devices to the memory map
Update register read and write functions
Change-Id: I0007b496d2ae7264f4fa9f605d4b0a15fa747a0f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Define mc sid and txn override regs and sec cfgs.
Create array for mc sid override regs and sec config that is
used to initialize mc.
Add smmu ctx regs array to hold register values during suspend.
Change-Id: I7b265710a9ec2be7dea050058bce65c614772c78
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.
Change-Id: I3c18eb844963f39f91b5ac45e3709f3354bcda0c
Signed-off-by: Steven Kao <skao@nvidia.com>
This patch creates the base commit for the Tegra194 platform, from
Tegra186 code base.
Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This reverts commit c41df8fda84b9bc56bbb2347fb902f64b1bb557e
Fake system suspend relies on software running on EL3
to trigger a warm reset.
Revert enabling fake system suspend, as the software
running on El3 is not allowed to trigger a warm reset.
Change-Id: I6035f2a7bcb0a4ad50a62c5bc5239226c625ee5e
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
There are some platforms which uses MPIDR Affinity level 3 for storing
extra affinity information e.g. N1SDP uses it for keeping chip id in a
multichip setup, for such platforms MPIDR validation should not fail.
This patch adds Aff3 bits also as part of mpidr validation mask, for
platforms which does not uses Aff3 will not have any impact as these
bits will be all zeros.
Change-Id: Ia8273972fa7948fdb11708308d0239d2dc4dfa85
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.
timeout_init_us(some_timeout_us); returns a reference to detect
timeout for the provided microsecond delay value from current time.
timeout_elapsed(reference) return true/false whether the reference
timeout is elapsed.
Cherry picked from OP-TEE implementation [1].
[1] commit 33d30a74502b ("core: timeout detection support")
Minor:
- Remove stm32mp platform duplicated implementation.
- Add new include in marvell ble.mk
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c
a5ds only has always-on power domain and there is no power control
present. However, without the pwr_domain_off handler, the kernel
panics when the user will try to switch off secondary cores. The
a5ds_pwr_domain_off handler will prevent kernel from crashing,
i.e. the kernel will attempt but fail to shut down the secondary CPUs
if the user tries to switch them offline.
Change-Id: I3c2239a1b6f035113ddbdda063c8495000cbe30c
Signed-off-by: Usama Arif <usama.arif@arm.com>
This patch adds mapping for secure FLASH0 for qemu/virt and
qemu/qemu_sbsa platforms. This change is targeted for sbsa but since both
platforms share common code, changes in common defines was necessary.
For qemu_sbsa, this patch adds necessary mapping in order to boot without
semi-hosting from secure FLASH0. EFI need to stay in FLASH1 (share it with
variables) since it need to "run in place" in non secure domain. Changes
for this are under RFC at edk2-platforms mailing list:
https://patches.linaro.org/patch/171327/
(edk2-platforms/Platform/Qemu/SbsaQemu/SbsaQemu.dsc).
In docs qemu/virt is described as using semi-hosting, therefore this change
should be orthogonal to existing assumptions while giving possibility to
store both bl1 and fip in FLASH0 at some point (additional changes required
for that).
Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I782bc3637c91c01eaee680b3c5c408e24b4b6e28
This patch introduces Qemu SBSA platform.
Both platform specific files where copied from qemu/qemu with changes for
DRAM base above 32bit and removal of ARMv7 conditional defines/code.
Documentation is aligned to rest of SBSA patches along the series and
planed changes in edk2-platform repo.
FixesARM-software/tf-issues#602
Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I8ebc34eedb2268365e479ef05654b2df1b99128c
* changes:
stm32mp1: add authentication support for stm32image
bsec: move bsec_mode_is_closed_device() service to platform
crypto: stm32_hash: Add HASH driver
* changes:
amlogic: g12a: Add support for the S905X2 (G12A) platform
amlogic: makefile: Use PLAT variable when possible
amlogic: sha_dma: Move register mappings to platform header
* changes:
rpi4: Add initial documentation file
rpi4: Add stdout-path to device tree
rpi4: Add GIC maintenance interrupt to GIC DT node
rpi4: Cleanup memory regions, move pens to first page
rpi4: Reserve resident BL31 region from non-secure world
rpi4: Amend DTB to advertise PSCI
rpi4: Determine BL33 entry point at runtime
rpi4: Accommodate "armstub8.bin" header at the beginning of BL31 image
Add basic support for Raspberry Pi 4
rpi3: Allow runtime determination of UART base clock rate
FDT helper functions: Respect architecture in PSCI function IDs
FDT helper functions: Add function documentation
* changes:
Migrate ARM platforms to use the new GICv3 API
Adding new optional PSCI hook pwr_domain_on_finish_late
GICv3: Enable multi socket GIC redistributor frame discovery
Introduce the preliminary support for the Amlogic S905X2 (G12A) SoC.
This port is a minimal implementation of BL31 capable of booting
mainline U-Boot and Linux. Tested on a SEI510 board.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ife958f10e815a4530292c45446adb71239f3367f
This patch invokes the new function gicv3_rdistif_probe() in the
ARM platform specific gicv3 driver. Since this API modifies the
shared GIC related data structure, it must be invoked coherently
by using the platform specific pwr_domain_on_finish_late hook.
Change-Id: I6efb17d5da61545a1c5a6641b8f58472b31e62a8
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Some device tree users like to find a pointer to the standard serial
console in the device tree, in the "stdout-path" property of the /chosen
node.
Add the location of the Mini UART in that property, so that DT users are
happy, for instance Linux' earlycon detection.
Change-Id: I178e55016e5640de5ab0bc6e061944bd3583ea96
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
For being able to use the virtualisation support the GIC offers, we need
to know the interrupt number of the maintenance interrupt. This
information is missing from the official RPi4 device tree.
Use libfdt to add the "interrupts" property to the GIC node, which
allows hypervisors like KVM or Xen to be able to use the GIC's help on
virtualising interrupts.
Change-Id: Iab84f0885a5bf29fb84ca8f385e8a39d27700c75
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Now that we have the SMP pens in the first page of DRAM, we can get rid
of all the fancy RPi3 memory regions that our RPi4 port does not really
need. This avoids using up memory all over the place, restricting ATF
to just run in the first 512KB of DRAM.
Remove the now unused regions. This also moves the SMP pens into our
first memory page (holding the firmware magic), where the original
firmware put them, but where there is also enough space for them.
Since the pens will require code execution privileges, we amend the
memory attributes used for that page to include write and execution
rights.
Change-Id: I131633abeb4a4d7b9057e737b9b0d163b73e47c6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The GPU firmware loads the armstub8.bin (BL31) image at address 0, the
beginning of DRAM. As this holds the resident PSCI code and the SMP
pens, the non-secure world should better know about this, to avoid
accessing memory owned by TF-A. This is particularly criticial as the
Raspberry Pi 4 does not feature a secure memory controller, so
overwriting code is a very real danger.
Use the newly introduced function to add a node into reserved-memory
node, where non-secure world can check for regions to be excluded from
its mappings.
Reserve the first 512KB of memory for now. We can refine this later if
need be.
Change-Id: I00e55e70c5c02615320d79ff35bc32b805d30770
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The device tree provided by the official Raspberry Pi firmware uses
spin tables for SMP bringup.
One of the benefit of having TF-A is that it provides PSCI services, so
let's rewrite the DTB to advertise PSCI instead of spin tables.
This uses the (newly exported) routine from the QEMU platform port.
Change-Id: Ifddcb14041ca253a333f8c2d5e97a42db152470c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Now that we have the armstub magic value in place, the GPU firmware will
write the kernel load address (and DTB address) into our special page,
so we can always easily access the actual location without hardcoding
any addresses into the BL31 image.
Make the compile-time defined PRELOADED_BL33_BASE macro optional, and
read the BL33 entry point from the magic location, if the macro was not
defined. We do the same for the DTB address.
This also splits the currently "common" definition of
plat_get_ns_image_entrypoint() to be separate between RPi3 and RPi4.
Change-Id: I6f26c0adc6fce2df47786b271c490928b4529abb
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The Raspberry Pi GPU firmware checks for a magic value at offset 240
(0xf0) of the armstub8.bin image it loads. If that value matches,
it writes the kernel load address and the DTB address into subsequent
memory locations.
We can use these addresses to avoid hardcoding these values into the BL31
image, to make it more flexible and a drop-in replacement for the
official armstub8.bin.
Reserving just 16 bytes at offset 240 of the final image file is not easily
possible, though, as this location is in the middle of the generic BL31
entry point code.
However we can prepend an extra section before the actual BL31 image, to
contain the magic and addresses. This needs to be 4KB, because the
actual BL31 entry point needs to be page aligned.
Use the platform linker script hook that the generic code provides, to
add an almost empty 4KB code block before the entry point code. The very
first word contains a branch instruction to jump over this page, into
the actual entry code.
This also gives us plenty of room for the SMP pens later.
Change-Id: I38caa5e7195fa39cbef8600933a03d86f09263d6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The Raspberry Pi 4 is a single board computer with four Cortex-A72
cores. From a TF-A perspective it is quite similar to the Raspberry Pi
3, although it comes with more memory (up to 4GB) and has a GIC.
This initial port though differs quite a lot from the existing rpi3
platform port, mainly due to taking a much simpler and more robust
approach to loading the non-secure payload:
The GPU firmware of the SoC, which is responsible for initial platform
setup (including DRAM initialisation), already loads the kernel, device
tree and the "armstub" into DRAM. We take advantage of this, by placing
just a BL31 component into the armstub8.bin component, which will be
executed first, in AArch64 EL3.
The non-secure payload can be a kernel or a boot loader (U-Boot or
EDK-2), disguised as the "kernel" image and loaded by the GPU firmware.
So this is just a BL31-only port, which directly drops into EL2
and executes whatever has been loaded as the "kernel" image, handing
over the DTB address in x0.
Change-Id: I636f4d1f661821566ad9e341d69ba36f6bbfb546
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
At the moment the UART input clock rate is hard coded at compile time.
This works as long as the GPU firmware always sets up the same rate,
which does not seem to be true for the Raspberry Pi 4.
In preparation for being able to change this at runtime, add a base
clock parameter to the console setup function. This is still hardcoded
for the Raspberry Pi 3.
Change-Id: I398bc2f1e9b46f7af9a84cb0b33cbe8e78f2d900
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The Fast Models provide a non-volatile counter component, which is used
in the Trusted Board Boot implementation to protect against rollback
attacks.
This component comes in 2 versions (see [1]).
- Version 0 is the default and models a locked non-volatile counter,
whose value is fixed.
- Version 1 of the counter may be incremented in a monotonic fashion.
plat_set_nv_ctr() must cope with both versions. This is achieved by:
1) Attempting to write the new value in the counter.
2) Reading the value back.
3) If there is a mismatch, we know the counter upgrade failed.
When using version 0 of the counter, no upgrade is possible so the
function is expected to fail all the time. However, the code is
missing a compiler barrier between the write operation and the next
read. Thus, the compiler may optimize and remove the read operation on
the basis that the counter value has not changed. With the default
optimization level used in TF-A (-Os), this is what's happening.
The fix introduced in this patch marks the write and subsequent read
accesses to the counter as volatile, such that the compiler makes no
assumption about the value of the counter.
Note that the comment above plat_set_nv_ctr() was clearly stating
that when using the read-only version of the non-volatile counter,
"we expect the values in the certificates to always match the RO
values so that this function is never called". However, the fact that
the counter value was read back seems to contradict this comment, as
it is implementing a counter-measure against misuse of the
function. The comment has been reworded to avoid any confusion.
Without this patch, this bug may be demonstrated on the Base AEM FVP:
- Using version 0 of the non-volatile counter (default version).
- With certificates embedding a revision number value of 32
(compiling TF-A with TFW_NVCTR_VAL=32).
In this configuration, the non-volatile counter is tied to value 31 by
default. When BL1 loads the Trusted Boot Firmware certificate, it
notices that the two values do not match and tries to upgrade the
non-volatile counter. This write operation is expected to fail
(because the counter is locked) and the function is expected to return
an error but it succeeds instead.
As a result, the trusted boot does not abort as soon as it should and
incorrectly boots BL2. The boot is finally aborted when BL2 verifies
the BL31 image and figures out that the version of the SoC Firmware
Key Certificate does not match. On Arm platforms, only certificates
signed with the Root-of-Trust Key may trigger an upgrade of the
non-volatile Trusted counter.
[1] https://developer.arm.com/docs/100964/1160/fast-models-components/peripheral-components/nonvolatilecounter
Change-Id: I9979f29c23b47b338b9b484013d1fb86c59db92f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Enable cores 1-3 using psci. On receiving the smc call from kernel,
core 0 will bring the secondary cores out pen and signal an event for
the cores. Currently on switching the cores is enabled i.e. it is not
possible to suspend, switch cores off, etc.
Change-Id: I6087e1d2ec650e1d587fd543efc1b08cbb50ae5f
Signed-off-by: Usama Arif <usama.arif@arm.com>
For the secondary CPUs, hold the cpu in wfe rather then panic.
This will be needed when multicore support is added to a5ds as
the smc call will write to the hold base and signal an event to
power on the secondary CPUs.
Change-Id: I0ffc2059e9ef894c21375ca5c94def859bfa6599
Signed-off-by: Usama Arif <usama.arif@arm.com>
This commit adds authentication binary support for STM32MP1.
It prints the bootrom authentication result if signed
image is used and authenticates the next loaded STM32 images.
It also enables the dynamic translation table support
(PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51
This BSEC service is a platform specific service. Implementation
moved to the platform part.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I1f70ed48a446860498ed111acce01187568538c9
Rockchip platform is using the first 1MB of DRAM as secure ram space,
and there is a vendor loader who loads and runs the BL31/BL32/BL33,
this loader is usually load by SoC BootRom to the start addres of DRAM,
we need to reserve enough space for this loader so that it doesn't need
to do the relocate when loading the BL31. eg.
We use U-Boot SPL to load ATF BL31 and U-Boot proper as BL33, the SPL
TEXT BASE is offset 0 of DRAM which is decide by Bootrom; if we update
the BL31_BASE to offset 0x40000(256KB), then the 0~0x40000 should be
enough for SPL and no need to do the relocate while the space size
0x10000(64KB) may not enough for SPL.
After this update, the BL31 can use the rest 768KB of the first 1MB,
which is also enough, and the loader who is using BL31 elf file can
support this update without any change.
Change-Id: I66dc685594d77f10f9a49c3be015fd6729250ece
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Patch introduce the macro NS_IMAGE_MAX_SIZE to simplify the image size
calculation. Use of additional parenthesis removes the possibility of
improper calculations due nested macro expansion for subtraction.
In case of platforms with DRAM window over 32bits, patch also removes
potential problems with type casting, as meminfo.image_size is uint32_t
but macro calculations were done in 64bit space.
Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I2d05a2d9dd6000dba6114df53262995cf85af018
This commit change the plat/qemu directory structure into:
`-- plat
`-- qemu
|-- common (files shared with all qemu subplatforms)
|-- qemu (original qemu platform)
|-- qemu_sbsa (new sqemu_sbsa platform)
|-- subplat1
`-- subplat2
This opens the possibility of adding new qemu sub-platforms which reuse
existing common platform code. The first platform which will leverage new
structure will be SBSA platform.
Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Id0d8133e1fffc1b574b69aa2770ebc02bb837a9b
Avoid to load FIP by hacking address. Load it by partition table instead.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Change-Id: I0283fc2e6e459bff14de19d92db4158e05106ee4
Avoid to load FIP by hacking address. Load it by partition table instead.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Change-Id: Ib476d024a51e4b9705441a0007d78f9fdf0ca078
The registers location for the SHA DMA driver is not unique for the
different platforms. Move the mapping out of the driver and into the
platform-specific header.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ice64637844a3cb384b01e466cb8c1cea5f764129
Both kernel and U-Boot use a SMC call to the secure monitor to get the
chip ID. This call is translated by BL31 to a call to the SCP to
retrieve the ID. Add a new SiP call and the backing SCPI command.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ib128f5645ee92866e7ebbcd550dacd33f573524b
* changes:
rpi3: Do prescaler and control setup in C
rpi3: Prepare for supporting a GIC (in RPi4)
rpi3: Make SHARED_RAM optional
rpi3: Rename RPI3_IO_BASE to RPI_IO_BASE
rpi3: Move shared rpi3 files into common directory
Hadi Asyrafi
Paul Kocialkowski
Lionel Debieve
Soby Mathew
James Liao
kenny liang
joanna.farley
Alexei Fedorov
Justin Chadwell
Max Shvetsov
Sandrine Bailleux
Louis Mayencourt
Vasily Khoruzhick
Imre Kis
Harvey Hsieh
Varun Wadekar
Anthony Zhou
Vignesh Radhakrishnan
Tejal Kudav
Paul Beesley
Manish Pandey
Roger Lu
Vijayenthiran Subramaniam
Andrew F. Davis
Steven Kao
Stefan Kristiansson
Rohit Khanna
Pritesh Raithatha
Usama Arif
Radoslaw Biernacki
Artsem Artsemenka
Carlo Caione
Madhukar Pappireddy
Andre Przywara
Kever Yang
Haojian Zhuang