Commit Graph

1179 Commits

Author SHA1 Message Date
Bipin Ravi e7ca4433fa fix(errata): workaround for Cortex-X2 errata 2017096
Cortex-X2 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0. The workaround is to set CPUECLTR_EL1[8]
to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I3b740aedc95c2394f6b8d1186014d2b2f640ae05
2022-02-06 01:43:39 -06:00
Daniel Boulby 7d33ffe4c1 fix(el3-runtime): set unset pstate bits to default
During a transition to a higher EL some of the PSTATE bits are not set
by hardware, this means that their state may be leaked from lower ELs.
This patch sets those bits to a default value upon entry to EL3.

This patch was tested using a debugger to check the PSTATE values
are correctly set. As well as adding a test in the next patch to
ensure the PSTATE in lower ELs is still maintained after this change.

Change-Id: Ie546acbca7b9aa3c86bd68185edded91b2a64ae5
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2022-02-03 11:33:49 +00:00
Daniel Boulby 97215e0f25 refactor(el3-runtime): add prepare_el3_entry func
In the next patch we add an extra step of setting the PSTATE
registers to a known state on el3 entry. In this patch we create
the function prepare_el3_entry to wrap the steps needed for before
el3 entry. For now this is only save_gp_pmcr_pauth_regs.

Change-Id: Ie26dc8d89bfaec308769165d2649e84d41be196c
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2022-01-31 11:27:11 +00:00
Jayanth Dodderi Chidanand 1471475516 feat(cpu): add library support for Poseidon CPU
This patch adds the basic CPU library code to support the Poseidon CPU
in TF-A. Poseidon is derived from HunterELP core, an implementation of
v9.2 architecture. Currently, Hunter CPU the predecessor to HunterELP,
is supported in TF-A. Accordingly the Hunter CPU library code has been
as the base and adapted here.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I406b4de156a67132e6a5523370115aaac933f18d
2022-01-28 11:12:21 +00:00
Manoj Kumar a72144fb7a fix(errata): workaround for Rainier erratum 1868343
Rainier CPU is based on Neoverse N1 R4P0 version which exhibits
the erratum 1868343. This patch inherits the workaround from
neoverse_n1.S file into rainier.S file for erratum 1868343.

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Change-Id: I735595229716a77d26369943086de08384cafa70
2022-01-05 17:16:19 +00:00
Joanna Farley a006606f3c Merge "feat(ccidx): update the do_dcsw_op function to support FEAT_CCIDX" into integration 2021-12-24 11:26:32 +01:00
johpow01 e16045de50 fix(errata): workaround for Cortex X2 erratum 2058056
Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.

There are 2 ways this workaround can be accomplished, the first of
which involves executing a few additional instructions around MSR
writes to CPUECTLR when disabling the prefetcher. (see SDEN for
details)

However, this patch implements the 2nd possible workaround which sets
the prefetcher into its most conservative mode, since this workaround
is generic.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Idb20d9928c986616cd5bedf40bb29d46d384cfd3
2021-12-21 11:52:26 -06:00
johpow01 34ee76dbdf fix(errata): workaround for Cortex X2 erratum 2002765
Cortex X2 erratum 2002765 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I11576a03bfd8a6b1bd9ffef4430a097d763ca3cf
2021-12-17 18:23:59 +01:00
johpow01 1db6cd6027 fix(errata): workaround for Cortex X2 erratum 2083908
Cortex X2 erratum 2083908 is a Cat B erratum present in the Cortex
X2 core. It applies to revision r2p0 and is still open.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Id9dca2b042bf48e75fb3013ab37d1c5925824728
2021-12-16 23:22:27 +01:00
johpow01 d0ec1cc437 feat(ccidx): update the do_dcsw_op function to support FEAT_CCIDX
FEAT_CCIDX modifies the register fields in CCSIDR/CCSIDR2 (aarch32)
and CCSIDR_EL1 (aarch64). This patch adds a check to the do_dcsw_op
function to use the right register format rather than assuming
that FEAT_CCIDX is not implemented.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I12cd00cd7b5889525d4d2750281a751dd74ef5dc
2021-12-14 12:48:08 -06:00
Yann Gautier 9e3f409398 feat(fconf): add a helper to get image index
A new function dyn_cfg_dtb_info_get_index() is created to get the index
of the given image config_id in the dtb_infos pool.
This allows checking if an image with a specific ID is in the FIP.

Change-Id: Ib300ed08e5b8a683dc7980a90221c305fb3f457d
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-13 17:37:53 +01:00
Jayanth Dodderi Chidanand f74cb0be8a fix(amu): fault handling on EL2 context switch
The HAFGRTR_EL2 register is UNDEFINED unless the CPU supports both
FEAT_FGT and FEAT_AMUv1. FEAT_FGT is mandatory for v8.6-A and upwards,
but FEAT_AMUv1 is optional (from v8.4-A upwards), and as such any
8.6-A cores today without support for FEAT_AMUv1 will trigger an
undefined instruction exception on accessing this register.

Currently ARM_ARCH_AT_LEAST macro has been used to associate with an
architecture extension allowing to access HAFGRTR_EL2 register. This
condition should be replaced with macros specific to individual
features. This patch adds a new set of macros "ENABLE_FEAT_FGT,
ENABLE_FEAT_AMUv1, ENABLE_FEAT_ECV" under build options to provide
controlled access to the HAFGRTR_EL2 register.

Further to ensure that the the build options passed comply
with the given hardware implementation, a feature detection mechanism,
checking whether build options match with the architecture is required
at bootime. This will be implemented and pushed later in a separate
patch.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie390f4babe233b8b09455290277edbddecd33ead
2021-12-10 12:33:51 +00:00
Madhukar Pappireddy 8b0c6612f1 Merge "fix(xlat): fix bug on VERBOSE trace" into integration 2021-12-06 19:00:38 +01:00
Javier Almansa Sobrino 956d76f69d fix(xlat): fix bug on VERBOSE trace
When log level is set to VERBOSE, a build error
happens due a incorrect format stringon a printf
call.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I8f869e078a3c179470977dadc063521c1ae30dbb
2021-12-03 10:31:17 +00:00
Yann Gautier 5ecde2a271 fix(pie): align fixup_gdt_reloc() for aarch64
Do not skip upper limit address (__RW_END__) during relocation process.
This align the code on what is done for AARCH32.

Change-Id: I236368376276c2d3aa79adce13ca49f4023ce369
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-01 17:35:33 +01:00
Yann Gautier 4f1a658f89 fix(pie): do not skip __RW_END__ address during relocation
In fixup_gdt_reloc(), do not skip the last address (__RW_END__) for
dynamic relocations.
Else, the invalidation of the data done under _init_c_runtime in
el3_entrypoint_common macro will not be correct.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I1166a59ac964ec8ad4e099cb3600e843afc71d82
2021-12-01 17:35:27 +01:00
johpow01 322b344e30 fix(rme): fixes a shift by 64 bits bug in the RME GPT library
Under certain configurations of PPS and L0GPTSZ a macro could result in
a right shift by 64 bits. This patch removes that possibility by
limiting the total size of each shift to the maximum width of the L0 or
L1 index field in a physical address. In addition, it adds more detail
about how these values are calculated.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ie71c8e6f922a5bb522a6169701bfc36fc99f765a
2021-11-16 17:41:43 +01:00
johpow01 dc78e62d80 feat(sme): enable SME functionality
This patch adds two new compile time options to enable SME in TF-A:
ENABLE_SME_FOR_NS and ENABLE_SME_FOR_SWD for use in non-secure and
secure worlds respectively. Setting ENABLE_SME_FOR_NS=1 will enable
SME for non-secure worlds and trap SME, SVE, and FPU/SIMD instructions
in secure context. Setting ENABLE_SME_FOR_SWD=1 will disable these
traps, but support for SME context management does not yet exist in
SPM so building with SPD=spmd will fail.

The existing ENABLE_SVE_FOR_NS and ENABLE_SVE_FOR_SWD options cannot
be used with SME as it is a superset of SVE and will enable SVE and
FPU/SIMD along with SME.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Iaaac9d22fe37b4a92315207891da848a8fd0ed73
2021-11-12 10:38:00 -06:00
Manish Pandey 2461bd3a89 fix(gpt_rme): use correct print format for uint64_t
sha 4ce3e99a3 introduced printf format specifiers for fixed width
types, which uses PRI*64 instead of "ll" for 64 bit values.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I30472411467061d58cc6ee22407ed3bad2552751
2021-11-09 20:58:03 +00:00
Manish Pandey 28623c102d Merge "fix: libc: use long for 64-bit types on aarch64" into integration 2021-11-08 21:34:42 +01:00
Scott Branden 4ce3e99a33 fix: libc: use long for 64-bit types on aarch64
Use long instead of long long on aarch64 for 64_t stdint types.
Introduce inttypes.h to properly support printf format specifiers for
fixed width types for such change.

Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
2021-11-08 14:41:17 +00:00
Madhukar Pappireddy 0b5e33c7aa Merge changes Ic2f90d79,Ieca02425,I615bcc1f,I6a9cb4a2,I5247f8f8, ... into integration
* changes:
  fix(errata): workaround for Neoverse V1 erratum 2216392
  fix(errata): workaround for Cortex A78 erratum 2242635
  fix(errata): workaround for Neoverse-N2 erratum 2280757
  fix(errata): workaround for Neoverse-N2 erratum 2242400
  fix(errata): workaround for Neoverse-N2 erratum 2138958
  fix(errata): workaround for Neoverse-N2 erratum 2242415
2021-11-08 15:28:19 +01:00
johpow01 4c8fe6b17f fix(errata): workaround for Neoverse V1 erratum 2216392
Neoverse V1 erratum 2216392 is a Cat B erratum present in the V1 core.
It applies to revisions r1p0 and r1p1 and is still open. The issue is
also present in r0p0 but there is no workaround in that revision.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic2f90d79c75e8ffef01aac81eddf1bfd8b7164ab
2021-11-05 23:10:58 +01:00
johpow01 1ea9190c6a fix(errata): workaround for Cortex A78 erratum 2242635
Cortex A78 erratum 2242635 is a Cat B erratum present in the A78 Core.
It applies to revisions r1p0, r1p1, r1p2, and is still open. The issue
is also present in r0p0 but there is no workaround for this revision.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ieca024254cabbc683ff13a70f3aeb8f2f3c5ce07
2021-11-05 20:52:41 +02:00
Soby Mathew 08da187682 Merge "fix(gpt_rme): add necessary barriers and remove cache clean" into integration 2021-11-05 10:35:56 +01:00
Soby Mathew 77612b90ac fix(gpt_rme): add necessary barriers and remove cache clean
This patch adds necessary barriers after GPT entries are modified
so that the writes are observed correctly by the GPC hardware.
The shareability of GPC fetches are changed from OSH to ISH so
that they align with the shareability of MMU attributes for the
region. Thus by adding a dsbishst() between the GPT L1 entry
write as part of granule migration at runtime, we can now remove
the clean cache maintenance operation (CMO) for that region.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Robert Wakim <robert.wakim@arm.com>
Change-Id: Ib9e405b106f0db95c7fbdb26773c0ed41663a5b4
2021-11-05 09:33:03 +00:00
nayanpatel-arm 0d2d99924e fix(errata): workaround for Neoverse-N2 erratum 2280757
Neoverse-N2 erratum 2280757 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR_EL1[22] to 1'b1. Setting CPUACTLR_EL1[22]
will cause CFP instruction to invalidate all branch predictor
resources regardless of context.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I615bcc1f993c45659b8b6f1a34fca0eb490f8add
2021-11-04 13:01:13 -07:00
nayanpatel-arm 603806d137 fix(errata): workaround for Neoverse-N2 erratum 2242400
Neoverse-N2 erratum 2242400 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR5_EL1[17] to 1'b1 followed by setting few
system control registers to specific values as per attached
SDEN document.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I6a9cb4a23238b8b511802a1ee9fcc5b207137649
2021-11-04 12:51:26 -07:00
nayanpatel-arm c948185c97 fix(errata): workaround for Neoverse-N2 erratum 2138958
Neoverse-N2 erratum 2138958 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR5_EL1[13] to 1'b1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I5247f8f8eef08d38c169aad6d2c5501ac387c720
2021-11-04 20:30:19 +01:00
nayanpatel-arm 5819e23bc4 fix(errata): workaround for Neoverse-N2 erratum 2242415
Neoverse-N2 erratum 2242415 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR_EL1[22] to 1'b1. Setting CPUACTLR_EL1[22]
will cause CFP instruction to invalidate all branch predictor
resources regardless of context.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I442be81fbc32e21fed51a84f59584df17f845e96
2021-11-04 12:13:22 -07:00
Chris Kay 2062a3936f fix(amu): remove `amu_fconf.c`
This file is unused and was introduced accidentally by one of the
commits in the MPMM patch stack. This functionality was instead
introduced by `fconf_amu_getter.c`.

Change-Id: Ib15b1114bacf9a2e7414c1fb35bd4fbdf0179210
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-01 11:13:24 +00:00
Manish Pandey 6482255d5d Merge "refactor(fvp_r): remove unused files and clean up makefiles" into integration 2021-10-29 18:48:52 +02:00
johpow01 88c227374c refactor(fvp_r): remove unused files and clean up makefiles
This patch removes files that are not used by TF-R as well as
removes unused generic files from the TF-R makefile.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Idb15ac295dc77fd38735bf2844efdb73e6f7c89b
2021-10-29 09:43:19 -05:00
Chris Kay 68120783d6 feat(mpmm): add support for MPMM
MPMM - the Maximum Power Mitigation Mechanism - is an optional
microarchitectural feature present on some Armv9-A cores, introduced
with the Cortex-X2, Cortex-A710 and Cortex-A510 cores.

MPMM allows the SoC firmware to detect and limit high activity events
to assist in SoC processor power domain dynamic power budgeting and
limit the triggering of whole-rail (i.e. clock chopping) responses to
overcurrent conditions.

This feature is enabled via the `ENABLE_MPMM` build option.
Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or
by via the plaform-implemented `plat_mpmm_topology` function.

Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-10-26 12:15:42 +01:00
Chris Kay 742ca2307f feat(amu): enable per-core AMU auxiliary counters
This change makes AMU auxiliary counters configurable on a per-core
basis, controlled by `ENABLE_AMU_AUXILIARY_COUNTERS`.

Auxiliary counters can be described via the `HW_CONFIG` device tree if
the `ENABLE_AMU_FCONF` build option is enabled, or the platform must
otherwise implement the `plat_amu_topology` function.

A new phandle property for `cpu` nodes (`amu`) has been introduced to
the `HW_CONFIG` specification to allow CPUs to describe the view of
their own AMU:

```
cpu0: cpu@0 {
    ...

    amu = <&cpu0_amu>;
};
```

Multiple cores may share an `amu` handle if they implement the
same set of auxiliary counters.

AMU counters are described for one or more AMUs through the use of a new
`amus` node:

```
amus {
    cpu0_amu: amu-0 {
        #address-cells = <1>;
        #size-cells = <0>;

        counter@0 {
            reg = <0>;

            enable-at-el3;
        };

        counter@n {
            reg = <n>;

            ...
        };
    };
};
```

This structure describes the **auxiliary** (group 1) AMU counters.
Architected counters have architecturally-defined behaviour, and as
such do not require DTB entries.

These `counter` nodes support two properties:

- The `reg` property represents the counter register index.
- The presence of the `enable-at-el3` property determines whether
  the firmware should enable the counter prior to exiting EL3.

Change-Id: Ie43aee010518c5725a3b338a4899b0857caf4c28
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-10-26 12:15:33 +01:00
Chris Kay e747a59be4 refactor(amu): refactor enablement and context switching
This change represents a general refactoring to clean up old code that
has been adapted to account for changes required to enable dynamic
auxiliary counters.

Change-Id: Ia85e0518f3f65c765f07b34b67744fc869b9070d
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-10-26 12:14:33 +01:00
Chris Kay 31d3cc2570 refactor(amu): detect auxiliary counters at runtime
This change decouples the group 1 counter macros to facilitate dynamic
detection at runtime. These counters remain disabled - we will add
dynamic enablement of them in a later patch.

Change-Id: I820d05f228d440643bdfa308d030bd51ebc0b35a
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-10-26 12:14:33 +01:00
Chris Kay 81e2ff1f36 refactor(amu): detect architected counters at runtime
This change removes the `AMU_GROUP0_COUNTERS_MASK` and
`AMU_GROUP0_MAX_COUNTERS` preprocessor definitions, instead retrieving
the number of group 0 counters dynamically through `AMCGCR_EL0.CG0NC`.

Change-Id: I70e39c30fbd5df89b214276fac79cc8758a89f72
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-10-26 12:14:32 +01:00
Chris Kay 1fd685a74d refactor(amu): conditionally compile auxiliary counter support
This change reduces preprocessor dependencies on the
`AMU_GROUP1_NR_COUNTERS` and `AMU_GROUP1_COUNTERS_MASK` definitions, as
these values will eventually be discovered dynamically.

In their stead, we introduce the `ENABLE_AMU_AUXILIARY_COUNTERS` build
option, which will enable support for dynamically detecting and
enabling auxiliary AMU counters.

This substantially reduces the amount of memory used by platforms that
know ahead of time that they do not have any auxiliary AMU counters.

Change-Id: I3d998aff44ed5489af4857e337e97634d06e3ea1
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-10-26 12:14:32 +01:00
Chris Kay 33b9be6d75 refactor(amu): factor out register accesses
This change introduces a small set of register getters and setters to
avoid having to repeatedly mask and shift in complex code.

Change-Id: Ia372f60c5efb924cd6eeceb75112e635ad13d942
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-10-26 12:14:31 +01:00
Chris Kay b4b726ea86 refactor(amu)!: privatize unused AMU APIs
This change reduces the exposed surface area of the AMU API in order to
simplify the refactoring work in following patches. The functions and
definitions privatized by this change are not used by other parts of the
code-base today.

BREAKING CHANGE: The public AMU API has been reduced to enablement only
to facilitate refactoring work. These APIs were not previously used.

Change-Id: Ibf6174fb5b3949de3c4ba6847cce47d82a6bd08c
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-10-26 12:14:31 +01:00
Chris Kay 9b43d098d8 build(amu): introduce `amu.mk`
This change introduces the `amu.mk` Makefile, used to remove the need
to manually include AMU sources into the various build images.
Makefiles requiring the list of AMU sources are expected to include
this file and use `${AMU_SOURCES}` to retrieve them.

Change-Id: I3d174033ecdce6439a110d776f0c064c67abcfe0
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-10-26 12:14:30 +01:00
Chris Kay e04da4c8e1 build(fconf)!: clean up source collection
Including the FCONF Makefile today automatically places the FCONF
sources into the source list of the BL1 and BL2 images. This may be
undesirable if, for instance, FCONF is only required for BL31.

This change moves the BL1 and BL2 source appends out of the common
Makefile to where they are required.

BREAKING CHANGE: FCONF is no longer added to BL1 and BL2 automatically
when the FCONF Makefile (`fconf.mk`) is included. When including this
Makefile, consider whether you need to add `${FCONF_SOURCES}` and
`${FCONF_DYN_SOURCES}` to `BL1_SOURCES` and `BL2_SOURCES`.

Change-Id: Ic028eabb7437ae95a57c5bcb7821044d31755c77
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-10-26 12:14:29 +01:00
johpow01 4cb576a0c5 fix(cpu): correct Demeter CPU name
This patch changes Cortex Demeter to Neoverse Demeter.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7306d09ca60e101d0a96c9ceff9845422d75c160
2021-10-21 20:12:28 +02:00
johpow01 fb9e5f7bb7 feat(cpu): add support for Hunter CPU
This patch adds the basic CPU library code to support the Hunter CPU
in TF-A. This CPU is based on the Makalu core so that library code
was adapted as the basis for this patch.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I956b2dc0f43da7cec3e015252392e2694363e1b3
2021-10-20 20:05:59 +02:00
Manish Pandey 33d99fdb48 Merge "fix(lib/optee): correct signedness comparison" into integration 2021-10-19 22:22:55 +02:00
Manish Pandey 0271be0dab Merge "feat(psci): require validate_power_state to expose CPU_SUSPEND" into integration 2021-10-18 18:28:55 +02:00
Manish Pandey 392547c365 Merge "fix(errata_report): correct typo" into integration 2021-10-18 18:26:54 +02:00
Samuel Holland a1d5ac6a5a feat(psci): require validate_power_state to expose CPU_SUSPEND
psci_cpu_suspend unconditionally calls psci_validate_power_state, which
asserts that the platform implements ops->validate_power_state. To avoid
a failure at runtime, do not expose CPU_SUSPEND unless that callback is
implemented. This also allows a platform to provide SYSTEM_SUSPEND
without providing CPU_SUSPEND.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I5dafb7845f482ab3af03a9de562def41dd70189e
2021-10-15 14:13:54 +02:00
Manish V Badarkhe eab78e9ba4 refactor(measured_boot): remove passing of BL2 hash via device tree
Subsequent patches will provide a solution to do the BL2 hash measurement
and recording in BL1 itself, hence in preparation to adopt that solution
remove the logic of passing BL2 hash measurement to BL2 component
via TB_FW config.

Change-Id: Iff9b3d4c6a236a33b942898fcdf799cbab89b724
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-10-12 17:53:47 +01:00
Yann Gautier 21d2be83a2 fix(lib/optee): correct signedness comparison
Avoid compilation errors with -Wsign-compare :
"comparison of integer expressions of different signedness"
by changing type of num to uint32_t.
And change init_load_addr check.

Change-Id: I891e4a288a964ffdb52129813ba8652c5bcf85b2
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-10-07 18:08:01 +02:00
Soby Mathew 1d65121174 Merge changes from topic "za/feat_rme" into integration
* changes:
  refactor(gpt): productize and refactor GPT library
  feat(rme): disable Watchdog for Arm platforms if FEAT_RME enabled
  docs(rme): add build and run instructions for FEAT_RME
  fix(plat/fvp): bump BL2 stack size
  fix(plat/fvp): allow changing the kernel DTB load address
  refactor(plat/arm): rename ARM_DTB_DRAM_NS region macros
  refactor(plat/fvp): update FVP platform DTS for FEAT_RME
  feat(plat/arm): add GPT initialization code for Arm platforms
  feat(plat/fvp): add memory map for FVP platform for FEAT_RME
  refactor(plat/arm): modify memory region attributes to account for FEAT_RME
  feat(plat/fvp): add RMM image support for FVP platform
  feat(rme): add GPT Library
  feat(rme): add ENABLE_RME build option and support for RMM image
  refactor(makefile): remove BL prefixes in build macros
  feat(rme): add context management changes for FEAT_RME
  feat(rme): add Test Realm Payload (TRP)
  feat(rme): add RMM dispatcher (RMMD)
  feat(rme): run BL2 in root world when FEAT_RME is enabled
  feat(rme): add xlat table library changes for FEAT_RME
  feat(rme): add Realm security state definition
  feat(rme): add register definitions and helper functions for FEAT_RME
2021-10-06 19:44:28 +02:00
Yann Gautier 322e60a6c7 fix(errata_report): correct typo
Change wrong __arch64__ to __aarch64__.

Change-Id: I750fdb16958e0eadf8aebe24bec0e14488fa4787
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-10-06 17:35:39 +02:00
johpow01 f19dc624a1 refactor(gpt): productize and refactor GPT library
This patch updates and refactors the GPT library and fixes bugs.

- Support all combinations of PGS, PPS, and L0GPTSZ parameters.
- PPS and PGS are set at runtime, L0GPTSZ is read from GPCCR_EL3.
- Use compiler definitions to simplify code.
- Renaming functions to better suit intended uses.
- MMU enabled before GPT APIs called.
- Add comments to make function usage more clear in GPT library.
- Added _rme suffix to file names to differentiate better from the
  GPT file system code.
- Renamed gpt_defs.h to gpt_rme_private.h to better separate private
  and public code.
- Renamed gpt_core.c to gpt_rme.c to better conform to TF-A precedent.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I4cbb23b0f81e697baa9fb23ba458aa3f7d1ed919
2021-10-05 16:24:57 -05:00
Madhukar Pappireddy de278f333b Merge "fix(errata): workaround for Cortex-A710 erratum 2058056" into integration 2021-10-05 23:17:19 +02:00
Madhukar Pappireddy e2f4b434b0 Merge changes If7dec725,Iedcb84a7,Ife0a4bec into integration
* changes:
  errata: workaround for Cortex-A78 erratum 2132060
  errata: workaround for Neoverse-V1 erratum 2108267
  fix(errata): workaround for Neoverse-N2 erratum 2138953
2021-10-05 21:02:00 +02:00
Zelalem Aweke 1839012d5b feat(rme): add GPT Library
This patch introduces the Granule Protection Table (GPT)
library code. This implementation will be updated later to
be more flexible, as the current implementation is very rigid.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I3af824a28c6e9a5d36459c0c51d2d9bebfba1505
2021-10-05 11:56:00 -05:00
Zelalem Aweke c5ea4f8a66 feat(rme): add context management changes for FEAT_RME
This patch adds a new context for realm world and realm world
awareness in context management.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Change-Id: Ic17469393603e789d7adc025880346bc3d6233d7
2021-10-05 18:41:35 +02:00
Zelalem Aweke 6c09af9f8b feat(rme): run BL2 in root world when FEAT_RME is enabled
This patch enables BL2 to run in root world (EL3) which is
needed as per the security model of RME-enabled systems.

Using the existing BL2_AT_EL3 TF-A build option is not convenient
because that option assumes TF-A BL1 doesn't exist, which is not
the case for RME-enabled systems. For the purposes of RME, we use
a normal BL1 image but we also want to run BL2 in EL3 as normally as
possible, therefore rather than use the special bl2_entrypoint
function in bl2_el3_entrypoint.S, we use a new bl2_entrypoint
function (in bl2_rme_entrypoint.S) which doesn't need reset or
mailbox initialization code seen in the el3_entrypoint_common macro.

The patch also cleans up bl2_el3_entrypoint.S, moving the
bl2_run_next_image function to its own file to avoid duplicating
code.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I99821b4cd550cadcb701f4c0c4dc36da81c7ef55
2021-10-04 21:13:20 +02:00
Zelalem Aweke 362182386b feat(rme): add xlat table library changes for FEAT_RME
FEAT_RME adds a new bit (NSE) in the translation table descriptor
to determine the Physical Address Space (PAS) of an EL3 stage 1
translation according to the following mapping:

	TTD.NSE    TTD.NS  |  PAS
	=================================
	  0          0	   |  Secure
	  0	     1	   |  Non-secure
	  1	     0	   |  Root
	  1	     1	   |  Realm

This patch adds modifications to version 2 of the translation table
library accordingly. Bits 4 and 5 in mmap attribute are used to
determine the PAS.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I82790f6900b7a1ab9494c732eac7b9808a388103
2021-10-04 14:09:23 -05:00
Yann Gautier 74d720a026 fix(xlat): remove always true check in assert
This issue was found with Clang compiler:
lib/xlat_tables_v2/aarch32/xlat_tables_arch.c:206:34:
 error: result of comparison of constant 4294967296 with expression
 of type 'uintptr_t' (aka 'unsigned long') is always true
 [-Werror,-Wtautological-constant-out-of-range-compare]
                assert(virtual_addr_space_size <=
                ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~

On AARCH32, MAX_VIRT_ADDR_SPACE_SIZE is defined as 1 << 32, and a 32 bit
uintptr_t is always lower.
Just remove the assert line.

Change-Id: Iec2c05290cede6e9fedbbf7b7dff2118bd1f9b16
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-10-04 12:43:38 +02:00
Zelalem Aweke 81c272b3b7 feat(rme): add register definitions and helper functions for FEAT_RME
This patch adds new register and bit definitions for the Armv9-A
Realm Management Extension (RME) as described in the Arm
document DDI0615 (https://developer.arm.com/documentation/ddi0615/latest).

The patch also adds TLB maintenance functions and a function to
detect the presence of RME feature.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I03d2af7ea41a20a9e8a362a36b8099e3b4d18a11
2021-10-01 16:54:44 -05:00
nayanpatel-arm b36fe21243 errata: workaround for Cortex-A78 erratum 2132060
Cortex-A78 erratum 2132060 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, and r1p2 of CPU. It is still open.
The workaround is to write the value 2'b11 to the PF_MODE bits
in the CPUECTLR_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: If7dec72578633d37d110d103099e406c3a970ff7
2021-10-01 21:21:07 +02:00
nayanpatel-arm 8e140272fb errata: workaround for Neoverse-V1 erratum 2108267
Neoverse-V1 erratum 2108267 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r1p1 of CPU. It is still open. The
workaround is to write the value 2'b11 to the PF_MODE bits in
the CPUECTLR_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: Iedcb84a7ad34af7083116818f49d7296f7d9bf94
2021-10-01 21:17:04 +02:00
nayanpatel-arm ef8f0c52dd fix(errata): workaround for Neoverse-N2 erratum 2138953
Neoverse-N2 erratum 2138953 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: Ife0a4bece7ccf83cc99c1d5f5b5a43084bb69d64
2021-10-01 12:01:20 -07:00
nayanpatel-arm 744bdbf732 fix(errata): workaround for Cortex-A710 erratum 2058056
Cortex-A710 erratum 2058056 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r2p0. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I7ce5181b3b469fbbb16501e633116e119b8bf4f1
2021-10-01 20:32:00 +02:00
Bipin Ravi fe82bcc04a Merge "feat(cpu): add support for Hayes CPU" into integration 2021-09-30 23:10:09 +02:00
johpow01 7bd8dfb85a feat(cpu): add support for Hayes CPU
This patch adds the basic CPU library code to support the Hayes CPU
in TF-A. This CPU is based on the Klein core so that library code
has been adapted for use here.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If0e0070cfa77fee8f6eebfee13d3c4f209ad84fc
2021-09-30 19:30:39 +02:00
laurenw-arm e31fb0fa1b fvp_r: load, auth, and transfer from BL1 to BL33
Adding load, authentication, and transfer functionality from FVP R BL1 to
BL33, which will be the partner runtime code.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I293cad09739dacac0d20dd57c1d98178dbe84d40
2021-09-30 17:07:11 +01:00
Gary Morrison 5fb061e761 chore: fvp_r: Initial No-EL3 and MPU Implementation
For v8-R64, especially R82, creating code to run BL1 at EL2, using MPU.

Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I439ac3915b982ad1e61d24365bdd1584b3070425
2021-09-30 17:05:59 +01:00
Bipin Ravi 114785c9b2 Merge "errata: workaround for Cortex-A710 erratum 2083908" into integration 2021-09-29 21:31:59 +02:00
johpow01 cb4ec47b5c feat(hcx): add build option to enable FEAT_HCX
FEAT_HCX adds the extended hypervisor configuration register (HCRX_EL2)
and access to this register must be explicitly enabled through the
SCR_EL3.HXEn bit.  This patch adds a new build flag ENABLE_FEAT_HCX to
allow the register to be accessed from EL2.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ibb36ad90622f1dc857adab4b0d4d7a89456a522b
2021-09-27 17:07:52 +02:00
nayanpatel-arm 95fe195d53 errata: workaround for Cortex-A710 erratum 2083908
Cortex-A710 erratum 2083908 is a Cat B erratum that applies to
revision r2p0 and is still open. The workaround is to set
CPUACTLR5_EL1[13] to 1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I876d26a7ac6ab0d7c567a9ec9f34fc0f952589d8
2021-09-24 14:00:09 -07:00
Manish Pandey b3210f4ddb Merge changes from topic "TrcDbgExt" into integration
* changes:
  feat(plat/fvp): enable trace extension features by default
  feat(trf): enable trace filter control register access from lower NS EL
  feat(trf): initialize trap settings of trace filter control registers access
  feat(sys_reg_trace): enable trace system registers access from lower NS ELs
  feat(sys_reg_trace): initialize trap settings of trace system registers access
  feat(trbe): enable access to trace buffer control registers from lower NS EL
  feat(trbe): initialize trap settings of trace buffer control registers access
2021-09-17 11:36:43 +02:00
Etienne Carriere b84a850864 feat(lib/optee): introduce optee_header_is_valid()
This new function optee_header_is_valid() allows platform to know
whether OP-TEE OS is loaded from multi-image (using OP-TEE header
image as BL32_IMAGE_ID) or from a single OP-TEE binary image.
The function tee_validate_header() is reworked to return a boolean,
and is now silent.

Change-Id: Idc7dde091f2ada8898f40d02e68c3834ca39d8e8
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-09-06 13:21:54 +02:00
Madhukar Pappireddy ef03e78f42 Merge changes from topic "erratas" into integration
* changes:
  errata: workaround for Neoverse N2 erratum 2138956
  errata: workaround for Neoverse N2 erratum 2189731
  errata: workaround for Cortex-A710 erratum 2017096
  errata: workaround for Cortex-A710 erratum 2055002
2021-09-03 23:58:01 +02:00
Bipin Ravi 1cafb08deb errata: workaround for Neoverse N2 erratum 2138956
Neoverse N2 erratum 2138956 is a Cat B erratum that applies to
revision r0p0 and is still open. This erratum can be avoided by
inserting a sequence of 16 DMB ST instructions prior to WFI or WFE.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I1aac87b3075992f875451e4767b21857f596d0b2
2021-09-03 15:44:56 -05:00
Bipin Ravi 7cfae93227 errata: workaround for Neoverse N2 erratum 2189731
Neoverse N2 erratum 2189731 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR5_EL1[44] to 1 which will cause the CPP instruction to
invalidate the hardware prefetcher state trained from any EL.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Iddc6a59adf9fa3cab560c46f2133e1f5a8b3ad03
2021-09-03 15:44:56 -05:00
Bipin Ravi afc2ed63f9 errata: workaround for Cortex-A710 erratum 2017096
Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1[8] to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3
2021-09-03 15:44:56 -05:00
Bipin Ravi 213afde907 errata: workaround for Cortex-A710 erratum 2055002
Cortex-A710 erratum 2055002 is a Cat B erratum that applies to
revisions r1p0 & r2p0 and is still open. The workaround is to
set CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r1p0 & r2p0.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I67be1dce53c4651167d8cee33c116e73b9dafe81
2021-09-03 15:44:47 -05:00
Madhukar Pappireddy b7942a91b8 Merge changes from topic "erratas" into integration
* changes:
  errata: workaround for Neoverse N2 erratum 2025414
  errata: workaround for Neoverse N2 erratum 2067956
2021-09-03 21:31:00 +02:00
Madhukar Pappireddy 9dc2534fd7 Merge "errata: workaround for Cortex-A78 errata 1952683" into integration 2021-09-02 22:20:54 +02:00
Bipin Ravi 4618b2bfa7 errata: workaround for Neoverse N2 erratum 2025414
Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia1c63fb93a1bdb1c3f4cf019a197b2a59233885a
2021-09-02 11:00:13 -05:00
Bipin Ravi 65e04f27d4 errata: workaround for Neoverse N2 erratum 2067956
Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r0p0.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ie92d18a379c66675b5c1c50fd0b8dde130848b21
2021-09-02 10:52:50 -05:00
Madhukar Pappireddy 3c9962a1c0 Merge "errata: workaround for Neoverse-N2 errata 2002655" into integration 2021-08-31 00:14:24 +02:00
Madhukar Pappireddy 523569d09d Merge changes I1e8c2bc3,I9bcff306 into integration
* changes:
  errata: workaround for Cortex-A710 errata 2081180
  errata: workaround for Cortex-A710 errata 1987031
2021-08-31 00:02:49 +02:00
nayanpatel-arm 9380f75418 errata: workaround for Neoverse-N2 errata 2002655
Neoverse-N2 erratum 2002655 is a Cat B erratum present in r0p0 of
the Neoverse-N2 processor core, and it is still open.

Neoverse-N2 SDEN: https://documentation-service.arm.com/static/61098b4e3d73a34b640e32c9?token=

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I1380418146807527abd97cdd4918265949ba5c01
2021-08-30 22:31:55 +02:00
Varun Wadekar d0464435f6 Merge "feat(cpus): workaround for Cortex A78 AE erratum 1941500" into integration 2021-08-26 12:18:59 +02:00
Manish V Badarkhe 8fcd3d9600 feat(trf): enable trace filter control register access from lower NS EL
Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter
control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).

Change-Id: If3f53b8173a5573424b9a405a4bd8c206ffdeb8c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-26 09:32:35 +01:00
Manish V Badarkhe d4582d3088 feat(sys_reg_trace): enable trace system registers access from lower NS ELs
Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace
system registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).

Change-Id: Idc1acede4186e101758cbf7bed5af7b634d7d18d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-26 09:29:51 +01:00
Manish V Badarkhe 813524ea9d feat(trbe): enable access to trace buffer control registers from lower NS EL
Introduced a build flag 'ENABLE_TRBE_FOR_NS' to enable trace buffer
control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).

Change-Id: I285a672ccd395eebd377714c992bb21062a729cc
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-26 09:29:39 +01:00
nayanpatel-arm a64bcc2b45 errata: workaround for Cortex-A710 errata 2081180
Cortex-A710 erratum 2081180 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN: https://developer.arm.com/documentation/SDEN1775101/1000

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I1e8c2bc3d8dc326947ccfd91daf9083d666b2542
2021-08-25 17:35:15 -07:00
Manish V Badarkhe 40ff907470 feat(trbe): initialize trap settings of trace buffer control registers access
Trap bits of trace buffer control registers access are in
architecturally UNKNOWN state at boot hence

1. Initialized these bits to zero to prohibit trace buffer control
   registers accesses in lower ELs (EL2, EL1) in all security states
   when FEAT_TRBE is implemented
2. Also, these bits are RES0 when FEAT_TRBE is not implemented, and
   hence setting it to zero also aligns with the Arm ARM reference
   recommendation, that mentions software must writes RES0 bits with
   all 0s

Change-Id: If2752fd314881219f232f21d8e172a9c6d341ea1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-25 18:01:16 +01:00
Joanna Farley 6657c1e3cc Merge "cpu: add support for Demeter CPU" into integration 2021-08-25 10:30:29 +02:00
nayanpatel-arm fbcf54aeb9 errata: workaround for Cortex-A710 errata 1987031
Cortex-A710 erratum 1987031 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN: https://documentation-service.arm.com/static/61099dc59ebe3a7dbd3a8a88?token=

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I9bcff306f82328ad5a0f6e9836020d23c07f7179
2021-08-23 15:51:26 -07:00
nayanpatel-arm 00bee99761 errata: workaround for Cortex-A78 errata 1952683
Cortex-A78 erratum 1952683 is a Cat B erratum present in r0p0 of
the Cortex-A78 processor core, and it was fixed in r1p0.

A78 SDEN : https://developer.arm.com/documentation/SDEN1401784/1400

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I77b03e695532cb13e8f8d3f00c43d973781ceeb0
2021-08-23 12:19:29 -07:00
Varun Wadekar 47d6f5ff16 feat(cpus): workaround for Cortex A78 AE erratum 1941500
Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

This erratum is avoided by by setting CPUECTLR_EL1[8] to 1.
There is a small performance cost (<0.5%) for setting this
bit.

SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900

Change-Id: I2d72666468b146714a0340ba114ccf0f5165b39c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2021-08-19 02:15:09 -07:00
johpow01 f4616efafb cpu: add support for Demeter CPU
This patch adds the basic CPU library code to support the Demeter
CPU.  This CPU is based on the Makalu-ELP core so that CPU lib code
was adapted to create this patch.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib5740b748008a72788c557f0654d8d5e9ec0bb7f
2021-08-17 13:14:58 -05:00
Varun Wadekar 8913047a52 feat(cpus): workaround for Cortex A78 AE erratum 1951502
Cortex A78 AE erratum 1951502 is a Cat B erratum that applies to revisions
<= r0p1. It is still open. This erratum is avoided by inserting a DMB ST
before acquire atomic instructions without release semantics through a series
of writes to implementation defined system registers.

SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900

Change-Id: I812c5a37cdd03486df8af6046d9fa988f6a0a098
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2021-08-16 20:23:07 +01:00
johpow01 100d4029a9 errata: workaround for Neoverse V1 errata 2139242
Neoverse V1 erratum 2139242 is a Cat B erratum present in the V1
processor core.  This issue is present in revisions r0p0, r1p0,
and r1p1, and it is still open.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I5c2e9beec72a64ac4131fb6dd76199821a934ebe
2021-08-10 17:23:01 +02:00