Commit Graph

1179 Commits

Author SHA1 Message Date
Yann Gautier 21d2be83a2 fix(lib/optee): correct signedness comparison
Avoid compilation errors with -Wsign-compare :
"comparison of integer expressions of different signedness"
by changing type of num to uint32_t.
And change init_load_addr check.

Change-Id: I891e4a288a964ffdb52129813ba8652c5bcf85b2
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-10-07 18:08:01 +02:00
Soby Mathew 1d65121174 Merge changes from topic "za/feat_rme" into integration
* changes:
  refactor(gpt): productize and refactor GPT library
  feat(rme): disable Watchdog for Arm platforms if FEAT_RME enabled
  docs(rme): add build and run instructions for FEAT_RME
  fix(plat/fvp): bump BL2 stack size
  fix(plat/fvp): allow changing the kernel DTB load address
  refactor(plat/arm): rename ARM_DTB_DRAM_NS region macros
  refactor(plat/fvp): update FVP platform DTS for FEAT_RME
  feat(plat/arm): add GPT initialization code for Arm platforms
  feat(plat/fvp): add memory map for FVP platform for FEAT_RME
  refactor(plat/arm): modify memory region attributes to account for FEAT_RME
  feat(plat/fvp): add RMM image support for FVP platform
  feat(rme): add GPT Library
  feat(rme): add ENABLE_RME build option and support for RMM image
  refactor(makefile): remove BL prefixes in build macros
  feat(rme): add context management changes for FEAT_RME
  feat(rme): add Test Realm Payload (TRP)
  feat(rme): add RMM dispatcher (RMMD)
  feat(rme): run BL2 in root world when FEAT_RME is enabled
  feat(rme): add xlat table library changes for FEAT_RME
  feat(rme): add Realm security state definition
  feat(rme): add register definitions and helper functions for FEAT_RME
2021-10-06 19:44:28 +02:00
Yann Gautier 322e60a6c7 fix(errata_report): correct typo
Change wrong __arch64__ to __aarch64__.

Change-Id: I750fdb16958e0eadf8aebe24bec0e14488fa4787
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-10-06 17:35:39 +02:00
johpow01 f19dc624a1 refactor(gpt): productize and refactor GPT library
This patch updates and refactors the GPT library and fixes bugs.

- Support all combinations of PGS, PPS, and L0GPTSZ parameters.
- PPS and PGS are set at runtime, L0GPTSZ is read from GPCCR_EL3.
- Use compiler definitions to simplify code.
- Renaming functions to better suit intended uses.
- MMU enabled before GPT APIs called.
- Add comments to make function usage more clear in GPT library.
- Added _rme suffix to file names to differentiate better from the
  GPT file system code.
- Renamed gpt_defs.h to gpt_rme_private.h to better separate private
  and public code.
- Renamed gpt_core.c to gpt_rme.c to better conform to TF-A precedent.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I4cbb23b0f81e697baa9fb23ba458aa3f7d1ed919
2021-10-05 16:24:57 -05:00
Madhukar Pappireddy de278f333b Merge "fix(errata): workaround for Cortex-A710 erratum 2058056" into integration 2021-10-05 23:17:19 +02:00
Madhukar Pappireddy e2f4b434b0 Merge changes If7dec725,Iedcb84a7,Ife0a4bec into integration
* changes:
  errata: workaround for Cortex-A78 erratum 2132060
  errata: workaround for Neoverse-V1 erratum 2108267
  fix(errata): workaround for Neoverse-N2 erratum 2138953
2021-10-05 21:02:00 +02:00
Zelalem Aweke 1839012d5b feat(rme): add GPT Library
This patch introduces the Granule Protection Table (GPT)
library code. This implementation will be updated later to
be more flexible, as the current implementation is very rigid.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I3af824a28c6e9a5d36459c0c51d2d9bebfba1505
2021-10-05 11:56:00 -05:00
Zelalem Aweke c5ea4f8a66 feat(rme): add context management changes for FEAT_RME
This patch adds a new context for realm world and realm world
awareness in context management.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Change-Id: Ic17469393603e789d7adc025880346bc3d6233d7
2021-10-05 18:41:35 +02:00
Zelalem Aweke 6c09af9f8b feat(rme): run BL2 in root world when FEAT_RME is enabled
This patch enables BL2 to run in root world (EL3) which is
needed as per the security model of RME-enabled systems.

Using the existing BL2_AT_EL3 TF-A build option is not convenient
because that option assumes TF-A BL1 doesn't exist, which is not
the case for RME-enabled systems. For the purposes of RME, we use
a normal BL1 image but we also want to run BL2 in EL3 as normally as
possible, therefore rather than use the special bl2_entrypoint
function in bl2_el3_entrypoint.S, we use a new bl2_entrypoint
function (in bl2_rme_entrypoint.S) which doesn't need reset or
mailbox initialization code seen in the el3_entrypoint_common macro.

The patch also cleans up bl2_el3_entrypoint.S, moving the
bl2_run_next_image function to its own file to avoid duplicating
code.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I99821b4cd550cadcb701f4c0c4dc36da81c7ef55
2021-10-04 21:13:20 +02:00
Zelalem Aweke 362182386b feat(rme): add xlat table library changes for FEAT_RME
FEAT_RME adds a new bit (NSE) in the translation table descriptor
to determine the Physical Address Space (PAS) of an EL3 stage 1
translation according to the following mapping:

	TTD.NSE    TTD.NS  |  PAS
	=================================
	  0          0	   |  Secure
	  0	     1	   |  Non-secure
	  1	     0	   |  Root
	  1	     1	   |  Realm

This patch adds modifications to version 2 of the translation table
library accordingly. Bits 4 and 5 in mmap attribute are used to
determine the PAS.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I82790f6900b7a1ab9494c732eac7b9808a388103
2021-10-04 14:09:23 -05:00
Yann Gautier 74d720a026 fix(xlat): remove always true check in assert
This issue was found with Clang compiler:
lib/xlat_tables_v2/aarch32/xlat_tables_arch.c:206:34:
 error: result of comparison of constant 4294967296 with expression
 of type 'uintptr_t' (aka 'unsigned long') is always true
 [-Werror,-Wtautological-constant-out-of-range-compare]
                assert(virtual_addr_space_size <=
                ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~

On AARCH32, MAX_VIRT_ADDR_SPACE_SIZE is defined as 1 << 32, and a 32 bit
uintptr_t is always lower.
Just remove the assert line.

Change-Id: Iec2c05290cede6e9fedbbf7b7dff2118bd1f9b16
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-10-04 12:43:38 +02:00
Zelalem Aweke 81c272b3b7 feat(rme): add register definitions and helper functions for FEAT_RME
This patch adds new register and bit definitions for the Armv9-A
Realm Management Extension (RME) as described in the Arm
document DDI0615 (https://developer.arm.com/documentation/ddi0615/latest).

The patch also adds TLB maintenance functions and a function to
detect the presence of RME feature.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I03d2af7ea41a20a9e8a362a36b8099e3b4d18a11
2021-10-01 16:54:44 -05:00
nayanpatel-arm b36fe21243 errata: workaround for Cortex-A78 erratum 2132060
Cortex-A78 erratum 2132060 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, and r1p2 of CPU. It is still open.
The workaround is to write the value 2'b11 to the PF_MODE bits
in the CPUECTLR_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: If7dec72578633d37d110d103099e406c3a970ff7
2021-10-01 21:21:07 +02:00
nayanpatel-arm 8e140272fb errata: workaround for Neoverse-V1 erratum 2108267
Neoverse-V1 erratum 2108267 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r1p1 of CPU. It is still open. The
workaround is to write the value 2'b11 to the PF_MODE bits in
the CPUECTLR_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: Iedcb84a7ad34af7083116818f49d7296f7d9bf94
2021-10-01 21:17:04 +02:00
nayanpatel-arm ef8f0c52dd fix(errata): workaround for Neoverse-N2 erratum 2138953
Neoverse-N2 erratum 2138953 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: Ife0a4bece7ccf83cc99c1d5f5b5a43084bb69d64
2021-10-01 12:01:20 -07:00
nayanpatel-arm 744bdbf732 fix(errata): workaround for Cortex-A710 erratum 2058056
Cortex-A710 erratum 2058056 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r2p0. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I7ce5181b3b469fbbb16501e633116e119b8bf4f1
2021-10-01 20:32:00 +02:00
Bipin Ravi fe82bcc04a Merge "feat(cpu): add support for Hayes CPU" into integration 2021-09-30 23:10:09 +02:00
johpow01 7bd8dfb85a feat(cpu): add support for Hayes CPU
This patch adds the basic CPU library code to support the Hayes CPU
in TF-A. This CPU is based on the Klein core so that library code
has been adapted for use here.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If0e0070cfa77fee8f6eebfee13d3c4f209ad84fc
2021-09-30 19:30:39 +02:00
laurenw-arm e31fb0fa1b fvp_r: load, auth, and transfer from BL1 to BL33
Adding load, authentication, and transfer functionality from FVP R BL1 to
BL33, which will be the partner runtime code.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I293cad09739dacac0d20dd57c1d98178dbe84d40
2021-09-30 17:07:11 +01:00
Gary Morrison 5fb061e761 chore: fvp_r: Initial No-EL3 and MPU Implementation
For v8-R64, especially R82, creating code to run BL1 at EL2, using MPU.

Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I439ac3915b982ad1e61d24365bdd1584b3070425
2021-09-30 17:05:59 +01:00
Bipin Ravi 114785c9b2 Merge "errata: workaround for Cortex-A710 erratum 2083908" into integration 2021-09-29 21:31:59 +02:00
johpow01 cb4ec47b5c feat(hcx): add build option to enable FEAT_HCX
FEAT_HCX adds the extended hypervisor configuration register (HCRX_EL2)
and access to this register must be explicitly enabled through the
SCR_EL3.HXEn bit.  This patch adds a new build flag ENABLE_FEAT_HCX to
allow the register to be accessed from EL2.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ibb36ad90622f1dc857adab4b0d4d7a89456a522b
2021-09-27 17:07:52 +02:00
nayanpatel-arm 95fe195d53 errata: workaround for Cortex-A710 erratum 2083908
Cortex-A710 erratum 2083908 is a Cat B erratum that applies to
revision r2p0 and is still open. The workaround is to set
CPUACTLR5_EL1[13] to 1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I876d26a7ac6ab0d7c567a9ec9f34fc0f952589d8
2021-09-24 14:00:09 -07:00
Manish Pandey b3210f4ddb Merge changes from topic "TrcDbgExt" into integration
* changes:
  feat(plat/fvp): enable trace extension features by default
  feat(trf): enable trace filter control register access from lower NS EL
  feat(trf): initialize trap settings of trace filter control registers access
  feat(sys_reg_trace): enable trace system registers access from lower NS ELs
  feat(sys_reg_trace): initialize trap settings of trace system registers access
  feat(trbe): enable access to trace buffer control registers from lower NS EL
  feat(trbe): initialize trap settings of trace buffer control registers access
2021-09-17 11:36:43 +02:00
Etienne Carriere b84a850864 feat(lib/optee): introduce optee_header_is_valid()
This new function optee_header_is_valid() allows platform to know
whether OP-TEE OS is loaded from multi-image (using OP-TEE header
image as BL32_IMAGE_ID) or from a single OP-TEE binary image.
The function tee_validate_header() is reworked to return a boolean,
and is now silent.

Change-Id: Idc7dde091f2ada8898f40d02e68c3834ca39d8e8
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-09-06 13:21:54 +02:00
Madhukar Pappireddy ef03e78f42 Merge changes from topic "erratas" into integration
* changes:
  errata: workaround for Neoverse N2 erratum 2138956
  errata: workaround for Neoverse N2 erratum 2189731
  errata: workaround for Cortex-A710 erratum 2017096
  errata: workaround for Cortex-A710 erratum 2055002
2021-09-03 23:58:01 +02:00
Bipin Ravi 1cafb08deb errata: workaround for Neoverse N2 erratum 2138956
Neoverse N2 erratum 2138956 is a Cat B erratum that applies to
revision r0p0 and is still open. This erratum can be avoided by
inserting a sequence of 16 DMB ST instructions prior to WFI or WFE.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I1aac87b3075992f875451e4767b21857f596d0b2
2021-09-03 15:44:56 -05:00
Bipin Ravi 7cfae93227 errata: workaround for Neoverse N2 erratum 2189731
Neoverse N2 erratum 2189731 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR5_EL1[44] to 1 which will cause the CPP instruction to
invalidate the hardware prefetcher state trained from any EL.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Iddc6a59adf9fa3cab560c46f2133e1f5a8b3ad03
2021-09-03 15:44:56 -05:00
Bipin Ravi afc2ed63f9 errata: workaround for Cortex-A710 erratum 2017096
Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1[8] to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3
2021-09-03 15:44:56 -05:00
Bipin Ravi 213afde907 errata: workaround for Cortex-A710 erratum 2055002
Cortex-A710 erratum 2055002 is a Cat B erratum that applies to
revisions r1p0 & r2p0 and is still open. The workaround is to
set CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r1p0 & r2p0.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I67be1dce53c4651167d8cee33c116e73b9dafe81
2021-09-03 15:44:47 -05:00
Madhukar Pappireddy b7942a91b8 Merge changes from topic "erratas" into integration
* changes:
  errata: workaround for Neoverse N2 erratum 2025414
  errata: workaround for Neoverse N2 erratum 2067956
2021-09-03 21:31:00 +02:00
Madhukar Pappireddy 9dc2534fd7 Merge "errata: workaround for Cortex-A78 errata 1952683" into integration 2021-09-02 22:20:54 +02:00
Bipin Ravi 4618b2bfa7 errata: workaround for Neoverse N2 erratum 2025414
Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia1c63fb93a1bdb1c3f4cf019a197b2a59233885a
2021-09-02 11:00:13 -05:00
Bipin Ravi 65e04f27d4 errata: workaround for Neoverse N2 erratum 2067956
Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r0p0.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ie92d18a379c66675b5c1c50fd0b8dde130848b21
2021-09-02 10:52:50 -05:00
Madhukar Pappireddy 3c9962a1c0 Merge "errata: workaround for Neoverse-N2 errata 2002655" into integration 2021-08-31 00:14:24 +02:00
Madhukar Pappireddy 523569d09d Merge changes I1e8c2bc3,I9bcff306 into integration
* changes:
  errata: workaround for Cortex-A710 errata 2081180
  errata: workaround for Cortex-A710 errata 1987031
2021-08-31 00:02:49 +02:00
nayanpatel-arm 9380f75418 errata: workaround for Neoverse-N2 errata 2002655
Neoverse-N2 erratum 2002655 is a Cat B erratum present in r0p0 of
the Neoverse-N2 processor core, and it is still open.

Neoverse-N2 SDEN: https://documentation-service.arm.com/static/61098b4e3d73a34b640e32c9?token=

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I1380418146807527abd97cdd4918265949ba5c01
2021-08-30 22:31:55 +02:00
Varun Wadekar d0464435f6 Merge "feat(cpus): workaround for Cortex A78 AE erratum 1941500" into integration 2021-08-26 12:18:59 +02:00
Manish V Badarkhe 8fcd3d9600 feat(trf): enable trace filter control register access from lower NS EL
Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter
control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).

Change-Id: If3f53b8173a5573424b9a405a4bd8c206ffdeb8c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-26 09:32:35 +01:00
Manish V Badarkhe d4582d3088 feat(sys_reg_trace): enable trace system registers access from lower NS ELs
Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace
system registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).

Change-Id: Idc1acede4186e101758cbf7bed5af7b634d7d18d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-26 09:29:51 +01:00
Manish V Badarkhe 813524ea9d feat(trbe): enable access to trace buffer control registers from lower NS EL
Introduced a build flag 'ENABLE_TRBE_FOR_NS' to enable trace buffer
control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).

Change-Id: I285a672ccd395eebd377714c992bb21062a729cc
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-26 09:29:39 +01:00
nayanpatel-arm a64bcc2b45 errata: workaround for Cortex-A710 errata 2081180
Cortex-A710 erratum 2081180 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN: https://developer.arm.com/documentation/SDEN1775101/1000

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I1e8c2bc3d8dc326947ccfd91daf9083d666b2542
2021-08-25 17:35:15 -07:00
Manish V Badarkhe 40ff907470 feat(trbe): initialize trap settings of trace buffer control registers access
Trap bits of trace buffer control registers access are in
architecturally UNKNOWN state at boot hence

1. Initialized these bits to zero to prohibit trace buffer control
   registers accesses in lower ELs (EL2, EL1) in all security states
   when FEAT_TRBE is implemented
2. Also, these bits are RES0 when FEAT_TRBE is not implemented, and
   hence setting it to zero also aligns with the Arm ARM reference
   recommendation, that mentions software must writes RES0 bits with
   all 0s

Change-Id: If2752fd314881219f232f21d8e172a9c6d341ea1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-25 18:01:16 +01:00
Joanna Farley 6657c1e3cc Merge "cpu: add support for Demeter CPU" into integration 2021-08-25 10:30:29 +02:00
nayanpatel-arm fbcf54aeb9 errata: workaround for Cortex-A710 errata 1987031
Cortex-A710 erratum 1987031 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN: https://documentation-service.arm.com/static/61099dc59ebe3a7dbd3a8a88?token=

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I9bcff306f82328ad5a0f6e9836020d23c07f7179
2021-08-23 15:51:26 -07:00
nayanpatel-arm 00bee99761 errata: workaround for Cortex-A78 errata 1952683
Cortex-A78 erratum 1952683 is a Cat B erratum present in r0p0 of
the Cortex-A78 processor core, and it was fixed in r1p0.

A78 SDEN : https://developer.arm.com/documentation/SDEN1401784/1400

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I77b03e695532cb13e8f8d3f00c43d973781ceeb0
2021-08-23 12:19:29 -07:00
Varun Wadekar 47d6f5ff16 feat(cpus): workaround for Cortex A78 AE erratum 1941500
Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

This erratum is avoided by by setting CPUECTLR_EL1[8] to 1.
There is a small performance cost (<0.5%) for setting this
bit.

SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900

Change-Id: I2d72666468b146714a0340ba114ccf0f5165b39c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2021-08-19 02:15:09 -07:00
johpow01 f4616efafb cpu: add support for Demeter CPU
This patch adds the basic CPU library code to support the Demeter
CPU.  This CPU is based on the Makalu-ELP core so that CPU lib code
was adapted to create this patch.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib5740b748008a72788c557f0654d8d5e9ec0bb7f
2021-08-17 13:14:58 -05:00
Varun Wadekar 8913047a52 feat(cpus): workaround for Cortex A78 AE erratum 1951502
Cortex A78 AE erratum 1951502 is a Cat B erratum that applies to revisions
<= r0p1. It is still open. This erratum is avoided by inserting a DMB ST
before acquire atomic instructions without release semantics through a series
of writes to implementation defined system registers.

SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900

Change-Id: I812c5a37cdd03486df8af6046d9fa988f6a0a098
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2021-08-16 20:23:07 +01:00
johpow01 100d4029a9 errata: workaround for Neoverse V1 errata 2139242
Neoverse V1 erratum 2139242 is a Cat B erratum present in the V1
processor core.  This issue is present in revisions r0p0, r1p0,
and r1p1, and it is still open.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I5c2e9beec72a64ac4131fb6dd76199821a934ebe
2021-08-10 17:23:01 +02:00
johpow01 1a8804c383 errata: workaround for Neoverse V1 errata 1966096
Neoverse V1 erratum 1966096 is a Cat B erratum present in the V1
processor core.  This issue is present in revisions r0p0, r1p0,
and r1p1, but the workaround only applies to r1p0 and r1p1, it is still
open.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic0b9a931e38da8a7000648e221481e17c253563b
2021-08-10 10:22:00 -05:00
Bipin Ravi d1987f4c8f Merge "errata: workaround for Neoverse V1 errata 1925756" into integration 2021-08-10 00:32:05 +02:00
Bipin Ravi 55120f9ca6 Merge "errata: workaround for Neoverse V1 errata 1852267" into integration 2021-08-10 00:31:44 +02:00
Bipin Ravi 1d24eb33c5 Merge "errata: workaround for Neoverse V1 errata 1774420" into integration 2021-08-10 00:31:25 +02:00
laurenw-arm 741dd04c81 errata: workaround for Neoverse V1 errata 1925756
Neoverse V1 erratum 1925756 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the V1 processor core, and it is still open.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I6500dc98da92a7c405b9ae09d794d666e8f4ae52
2021-08-05 12:17:04 -05:00
laurenw-arm 143b19651b errata: workaround for Neoverse V1 errata 1852267
Neoverse V1 erratum 1852267 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ide5e0bc09371fbc91c2385ffdff74e604beb2dbe
2021-08-03 09:49:09 -05:00
laurenw-arm 4789cf66af errata: workaround for Neoverse V1 errata 1774420
Neoverse V1 erratum 1774420 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I66e27b2518f73faeedd8615a1443a74b6a30f123
2021-08-03 09:46:12 -05:00
Manish V Badarkhe f21693704a feat(sw_crc32): add software CRC32 support
Added software CRC32 support in case platform doesn't support
hardware CRC32.

Platform must include necessary Zlib source files for compilation
to use software CRC32 implementation.

Change-Id: Iecb649b2edf951944b1a7e4c250c40fe7a3bde25
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-02 17:15:41 +01:00
Arunachalam Ganapathy 68ac5ed049 fix(el3_runtime): fix SVE and AMU extension enablement flags
If SVE are enabled for both Non-secure and Secure world along with AMU
extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit
from bl31. This restricts access to the AMU register set in normal
world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT
by saving and restoring CPTR_EL3 register from EL3 context.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087
2021-07-23 10:33:59 +01:00
johpow01 182ce10155 errata: workaround for Neoverse V1 errata 1940577
Neoverse V1 erratum 1940577 is a Cat B erratum, present in some
revisions of the V1 processor core.  The workaround is to insert a
DMB ST before acquire atomic instructions without release semantics.
This issue is present in revisions r0p0 - r1p1  but this workaround
only applies to revisions r1p0 - r1p1, there is no workaround for older
versions.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I210ad7d8f31c81b6ac51b028dfbce75a725c11aa
2021-07-19 22:27:35 +01:00
johpow01 33e3e92541 errata: workaround for Neoverse V1 errata 1791573
Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic6f92da4d0b995bd04ca5b1673ffeedaebb71d10
2021-07-16 15:20:36 -05:00
Olivier Deprez 81a8b2da2c Merge "feat(sve): enable SVE for the secure world" into integration 2021-06-30 11:51:04 +02:00
Manish Pandey 204fd9913c Merge "errata: workaround for Cortex A77 errata 1791578" into integration 2021-06-29 22:44:29 +02:00
Max Shvetsov 0c5e7d1ce3 feat(sve): enable SVE for the secure world
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is configured during initial setup and then uses EL3
context save/restore routine to switch between SVE configurations for
different contexts.
Reset value of CPTR_EL3 changed to be most restrictive by default.

Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116
2021-06-28 13:24:24 +01:00
johpow01 1a691455d9 errata: workaround for Cortex A78 errata 1821534
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and
r1p0 of the A78 processor core, it is fixed in r1p1.

SDEN can be found here:
https://documentation-service.arm.com/static/603e3733492bde1625aa8780

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I71057c4b9625cd9edc1a06946b453cf16ae5ea2c
2021-06-24 00:01:33 +02:00
johpow01 3f0bec7c88 errata: workaround for Cortex A77 errata 1791578
Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the A77 processor core, it is still open.

SDEN can be found here:
https://documentation-service.arm.com/static/60a63a3c982fc7708ac1c8b1

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib4b963144f880002de308def12744b982d3df868
2021-06-23 14:26:06 -05:00
Mark Dykes 66bf006e28 Merge "fix(security): Set MDCR_EL3.MCCD bit" into integration 2021-06-08 18:26:52 +02:00
Olivier Deprez 2e61d6871c fix: random typos in tf-a code base
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id610f7e4398e799a2fbd74861274fd684c32db53
2021-06-03 09:31:10 +02:00
johpow01 c6ac4df622 fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs
This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to
Cortex A710, Cortex X2, and Cortex A510 respectively.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I056d3114210db71c2840a24562b51caf2546e195
2021-05-28 13:53:23 -05:00
Alexei Fedorov 12f6c06497 fix(security): Set MDCR_EL3.MCCD bit
This patch adds setting MDCR_EL3.MCCD in 'el3_arch_init_common'
macro to disable cycle counting by PMCCNTR_EL0 in EL3 when
FEAT_PMUv3p7 is implemented. This fixes failing test
'Leak PMU CYCLE counter values from EL3 on PSCI suspend SMC'
on FVP models with 'has_v8_7_pmu_extension' parameter set to
1 or 2.

Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Change-Id: I2ad3ef501b31ee11306f76cb5a61032ecfd0fbda
2021-05-14 12:19:54 +01:00
Manish Pandey 08e7cc533e Merge changes I15e7cc43,Id7411bd5,I92bafe70,I8f1c0658 into integration
* changes:
  stm32mp1: enable PIE for BL32
  stm32mp1: set BL sizes regardless of flags
  Add PIE support for AARCH32
  Avoid the use of linker *_SIZE__ macros
2021-04-29 13:57:31 +02:00
Manish Pandey 815794220b Merge changes I36e45c0a,I69c21293 into integration
* changes:
  plat/qemu: add "max" cpu support
  Add support for QEMU "max" CPU
2021-04-27 11:44:31 +02:00
Yann Gautier 4324a14bf5 Add PIE support for AARCH32
Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just
stubbed with _pie_fixup_size=0.
The changes are an adaptation for AARCH32 on what has been done for
PIE support on AARCH64.
The RELA_SECTION is redefined for AARCH32, as the created section is
.rel.dyn and the symbols are .rel*.

Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-04-21 15:05:57 +02:00
johpow01 97bc7f0dcc Add "_arm" suffix to Makalu ELP CPU lib
ELP processors can sometimes have different MIDR values or features so
we are adding the "_arm" suffix to differentiate the reference
implementation from other future versions.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ieea444288587c7c18a397d279ee4b22b7ad79e20
2021-04-20 17:14:31 -05:00
Leif Lindholm 5d764e05e4 Add support for QEMU "max" CPU
Enable basic support for QEMU "max" CPU.
The "max" CPU does not attampt to emulate any specific CPU, but rather
just enables all the functions emulated by QEMU.

Change-Id: I69c212932ef61433509662d0fefbabb1e9e71cf2
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
2021-04-13 12:31:40 +01:00
Madhukar Pappireddy de2dd4e70a Merge "lib/cpu: Workaround for Cortex A77 erratum 1946167" into integration 2021-04-07 23:12:00 +02:00
Olivier Deprez e729595fa9 Merge "Fix: Remove save/restore of EL2 timer registers" into integration 2021-04-07 21:25:26 +02:00
Max Shvetsov a7cf2743f3 Fix: Remove save/restore of EL2 timer registers
Since there is a secure and non-secure version of the timer registers
there is no need to preserve their context in EL3.
With that, following registers were removed from EL3 save/restore
routine:
	cnthps_ctl_el2
	cnthps_tval_el2
	cnthps_cval_el2
	cnthvs_ctl_el2
	cnthvs_tval_el2
	cnthvs_cval_el2
	cnthp_ctl_el2
	cnthp_cval_el2
	cnthp_tval_el2
	cnthv_ctl_el2
	cnthv_cval_el2
	cnthv_tval_el2

Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I6e2fc09c74a7375c4fccc11f12af4e39e6dc616b
2021-04-07 11:18:23 +01:00
laurenw-arm a492edc49c lib/cpu: Workaround for Cortex A77 erratum 1946167
Cortex A77 erratum 1946167 is a Cat B erratum that applies to revisions
<= r1p1. This erratum is avoided by inserting a DMB ST before acquire
atomic instructions without release semantics through a series of
writes to implementation defined system registers.

SDEN can be found here:
https://documentation-service.arm.com/static/600057a29b9c2d1bb22cd1be?token=

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I53e3b4fb7e7575ec83d75c2f132eda5ae0b4f01f
2021-04-06 10:20:55 -05:00
Bipin Ravi 0a144dd4ea Add Cortex_A78C CPU lib
Add basic support for Cortex_A78C CPU.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56
2021-03-31 16:02:35 -05:00
johpow01 cb090c1924 Add Makalu ELP CPU lib
Add basic support for Makalu ELP processor core.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7b1ddbb8dd43326ecb8ff188f6f8fcf239826a93
2021-03-24 12:53:18 -05:00
Usama Arif 614c14e778
cpus: add Matterhorn ELP ARM cpu library
Change-Id: Ie1acde619a5b21e09717c0e80befb6d53fd16607
Signed-off-by: Usama Arif <usama.arif@arm.com>
2021-03-10 16:09:31 +00:00
bipin.ravi 8ef06b6cdd Merge "Add Makalu CPU lib" into integration 2021-03-02 16:21:22 +01:00
Manish Pandey 0cd5d1d19d Merge "lib/extensions/ras: fix bug of binary search" into integration 2021-03-02 15:00:08 +01:00
johpow01 aaabf9789a Add Makalu CPU lib
Add basic support for Makalu CPU.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I4e85d425eedea499adf585eb8ab548931185043d
2021-03-01 17:11:36 -06:00
johpow01 873d4241e3 Enable v8.6 AMU enhancements (FEAT_AMUv1p1)
ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0.  This patch enables support for this
feature in EL3 firmware.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217
2021-02-25 22:01:59 +00:00
Andre Przywara 005415a39a libc: memset: Fix MISRA issues
MISRA complained about "0"s not being followed by an "U" (please note
my protest about this!) and about values not being explicitly compared
to 0 (fair enough).
Also use explicit pointer types.

Fix those issues to make the CI happy.

Change-Id: I4d11e49c14f16223a71c78b0fc3e68ba9a1382d3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-02-24 09:33:59 +00:00
Yann Gautier e3b9cc1262 lib: cpus: aarch32: sanity check pointers before use
This is the AARCH32 update of patch [1].

 [1] 601e3ed209 ("lib: cpus: sanity check pointers before use")

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I43dbe00a5802a7e1c6f877e22d1c66ec8275c6fa
2021-02-23 15:16:51 +01:00
Madhukar Pappireddy 94b0c3341e Merge changes from topic "mp/strto_libc" into integration
* changes:
  libc: Import strtoull from FreeBSD project
  libc: Import strtoll from FreeBSD project
  libc: Import strtoul from FreeBSD project
  libc: Import strtol from FreeBSD project
2021-02-11 16:04:54 +00:00
Manoj Kumar 041d7c7ba9 rainier: remove cpu workaround for errata 1542419
This patch removes the Neoverse N1 CPU errata workaround for
bug 1542419 as the bug is not present in Rainier R0P0 core.

Change-Id: Icaca299b13ef830b2ee5129576aae655a6288e69
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
2021-02-05 11:14:58 +00:00
Madhukar Pappireddy d56b957c21 libc: Import strtoull from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.

Also made small changes to fit into TF-A project. Added the source
files to the libc makefile

[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution

Change-Id: I2e94a0b227ec39f6f4530dc50bb477999d27730f
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-02-03 10:36:33 -06:00
Madhukar Pappireddy 587c15565f libc: Import strtoll from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.

Also made small changes to fit into TF-A project. Added the source
files to the libc makefile

[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution

Change-Id: I9cb581574d46de73c3d6917ebf78935fc5ac075a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-02-03 10:36:33 -06:00
Madhukar Pappireddy 15c1c14735 libc: Import strtoul from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.

Also made small changes to fit into TF-A project. Added the source
files to the libc makefile

[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution

Change-Id: I8c3b92751d1ce226c966f7c81fedd83f0846865e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-02-03 10:36:33 -06:00
Madhukar Pappireddy 015240d9d3 libc: Import strtol from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.

Also made small changes to fit into TF-A project. Added the source
files to the libc makefile

[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution

Change-Id: Ica95bf5da722913834fe90bf3fe743aa34e01e80
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-02-03 10:36:33 -06:00
Madhukar Pappireddy c2d32a5f85 Fix exception handlers in BL31: Use DSB to synchronize pending EA
For SoCs which do not implement RAS, use DSB as a barrier to
synchronize pending external aborts at the entry and exit of
exception handlers. This is needed to isolate the SErrors to
appropriate context.

However, this introduces an unintended side effect as discussed
in the https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/3440
A summary of the side effect and a quick workaround is provided as
part of this patch and summarized here:

The explicit DSB at the entry of various exception vectors in BL31
for handling exceptions from lower ELs can inadvertently trigger an
SError exception in EL3 due to pending asyncrhonouus aborts in lower
ELs. This will end up being handled by serror_sp_elx in EL3 which will
ultimately panic and die.

The way to workaround is to update a flag to indicate if the exception
truly came from EL3. This flag is allocated in the cpu_context
structure. This is not a bullet proof solution to the problem at hand
because we assume the instructions following "isb" that help to update
the flag (lines 100-102 & 139-141) execute without causing further
exceptions.

Change-Id: I4d345b07d746a727459435ddd6abb37fda24a9bf
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-01-29 10:30:18 -06:00
Olivier Deprez 0ac8591df9 Merge "DebugFS: Check channel index before calling clone function" into integration 2021-01-22 17:34:56 +00:00
Zelalem b226c74737 DebugFS: Check channel index before calling clone function
To avoid a potential out-of-bounds access, check whether
a device exists on a channel before calling the corresponding
clone function.

Signed-off-by: Zelalem <zelalem.aweke@arm.com>
Change-Id: Ia0dd66b331d3fa8a33109a02369e1bc9ae0fdd5b
2021-01-21 15:25:23 +00:00
Heyi Guo 7981c5043b libc/snprintf: use macro to reduce duplicated code
Add macro CHECK_AND_PUT_CHAR to check buffer capacity, save one
character to buffer, and then increase character counter by one in one
single statement, so that 4 similar code pieces can be cleaned.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I2add6b4bd6c24ea3c0d2499a44924e3e8db0f4d1
2021-01-20 14:16:04 +08:00
Heyi Guo c654615466 libc/snprintf: add support to print "%" character
Enable snprintf()/vsnprintf() in TF-A to print "%" character as C
standard, which may be used in platform porting to print percentage
information.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I9b296372a1002046eabac1df5e8eb99a27efd4a8
2021-01-20 14:15:55 +08:00
Heyi Guo 128c5f0285 libc/printf: add support to print "%" character
Enable printf() in TF-A to print "%" character as C standard, which
may be used in platform porting to print percentage information.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I7af2f1d153548e426f423fce15dc48b0da56c622
2021-01-20 13:09:13 +08:00
Heyi Guo 0b1838a970 lib/extensions/ras: fix bug of binary search
In ras_interrupt_handler(), binary search end was set to the size of
the ras_interrupt_mappings array, which would cause out of bound
access when the input intr_raw is larger than all the elements in
ras_interrupt_mappings.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Id2cff73177134b09d4d8beb596c3429b98ec5066
2021-01-14 09:27:16 +08:00
johpow01 263ee781c6 Workaround for Cortex N1 erratum 1946160
Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1.  The workaround is to insert a DMB ST
before acquire atomic instructions without release semantics.  This
issue is present starting from r0p0 but this workaround applies to
revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no
workaround.

SDEN can be found here:
https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
2021-01-13 19:56:07 +00:00
johpow01 3a2710dcab Workaround for Cortex A78 erratum 1951500
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1.  The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics.  This workaround
works on revisions r1p0 and r1p1, in r0p0 there is no workaround.

SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
2021-01-13 13:54:18 -06:00
johpow01 e26c59d2c9 Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1.  The workaround is to set bit 8 in the ECTLR_EL1
register, there is a small performance cost (<0.5%) for setting this bit.

SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
2021-01-12 18:06:37 +00:00
Alexei Fedorov db9736e3d8 AArch64: Fix assertions in processing dynamic relocations
This patch provides the following changes in fixup_gdt_reloc()
function:
- Fixes assertions in processing dynamic relocations, when
relocation entries not matching R_AARCH64_RELATIVE type are found.
Linker might generate entries of relocation type R_AARCH64_NONE
(code 0), which should be ignored to make the code boot. Similar
issue was fixed in OP-TEE (see optee_os/ldelf/ta_elf_rel.c
commit 7a4dc765c133125428136a496a7644c6fec9b3c2)
- Fixes bug when "b.ge" (signed greater than or equal) condition
codes were used instead of "b.hs" (greater than or equal) for
comparison of absolute addresses.
- Adds optimisation which skips fixing Global Object Table (GOT)
entries when offset value is 0.

Change-Id: I35e34e055b7476843903859be947b883a1feb1b5
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2021-01-06 10:59:22 +00:00
Graeme Gregory a86865ac42 PSCI: fix limit of 256 CPUs caused by cast to unsigned char
In psci_setup.c psci_init_pwr_domain_node() takes an unsigned
char as node_idx which limits it to initialising only the first
256 CPUs. As the calling function does not check for a limit of
256 I think this is a bug so change the unsigned char to
uint16_t and change the cast from the calling site in
populate_power_domain_tree().

Also update the non_cpu_pwr_domain_node structure lock_index
to uint16_t and update the function signature for psci_lock_init()
appropriately.

Finally add a define PSCI_MAX_CPUS_INDEX to psci_private.h and add
a CASSERT to psci_setup.c to make sure PLATFORM_CORE_COUNT cannot
exceed the index value.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: I9e26842277db7483fd698b46bbac62aa86e71b45
2020-12-22 07:39:51 +00:00
johpow01 3f0d83695c Workaround for Cortex A76 erratum 1946160
Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions
of the A76 processor core.  The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics.  This issue is
present in revisions r0p0 - r4p1  but this workaround only applies to
revisions r3p0 - r4p1, there is no workaround for older versions.

SDEN can be found here:
https://documentation-service.arm.com/static/5fbb77d7d77dd807b9a80cc1

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ief33779ee76a89ce2649812ae5214b86a139e327
2020-12-18 17:41:23 +00:00
Javier Almansa Sobrino 0063dd1708 Add support for FEAT_MTPMU for Armv8.6
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happening on other threads.

If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit
leaving it to effective state of 0 regardless of any write to it.

This patch introduces the DISABLE_MTPMU flag, which allows to diable
multithread event count from EL3 (or EL2). The flag is disabled
by default so the behavior is consistent with those architectures
that do not implement FEAT_MTPMU.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
2020-12-11 12:49:20 +00:00
Alexei Fedorov 0563ab08e8 Aarch64: Add support for FEAT_MTE3
This patch provides the following changes:
- Adds definition for FEAT_MTE3 value in ID_AA64PFR1_EL1 register
- Enables Memory Tagging Extension for FEAT_MTE3.

Change-Id: I735988575466fdc083892ec12c1aee89b5faa472
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-12-02 13:53:03 +00:00
Javier Almansa Sobrino 25bbbd2d63 Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
2020-11-30 19:12:56 +00:00
johpow01 9bbc03a6e0 Revert workaround for A77 erratum 1800714
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.

This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4686

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I8554c75d7217331c7effd781b5f7f49b781bbebe
2020-11-12 14:15:41 -06:00
johpow01 95ed9a9e0d Revert workaround for A76 erratum 1800710
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.

This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4684

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I560749a5b55e22fbe49d3f428a8b9545d6bdaaf0
2020-11-12 13:55:43 -06:00
Arunachalam Ganapathy 2b036b7995 lib: el3_runtime: Fix SPE system registers in el2_sysregs_context
Include EL2 registers related to SPE in EL2 context save/restore
routines if architecture supports it and platform wants to use these
features in Secure world.

Change-Id: Ie01a2c38fa5f6c907276eddec120fdfb222561a6
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20 20:06:48 +00:00
Arunachalam Ganapathy 062f8aaf8a lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
Include EL2 registers related to Nested Virtualization in EL2 context
save/restore routines if architecture supports it and platform wants to
use these features in Secure world.

Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20 20:06:43 +00:00
Arunachalam Ganapathy 0f777eabd9 lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context
AArch64-only platforms do not implement AArch32 at EL1 and higher ELs.
In such cases the build option CTX_INCLUDE_AARCH32_REGS is set to 0.
So don't save/restore aarch32 system registers in el2_sysregs_context
save/restore routines if CTX_INCLUDE_AARCH32_REGS is set to 0.

Change-Id: I229cdd46136c4b4bc9623b02eb444d904e09ce5a
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20 20:06:36 +00:00
Joanna Farley 943aff0c16 Merge "Increase type widths to satisfy width requirements" into integration 2020-10-18 14:51:00 +00:00
Madhukar Pappireddy 4a6b33ec17 Merge changes Iba51bff1,I3f563cff into integration
* changes:
  plat:qti Mandate SMC implementaion and bug fix
  Update in coreboot_get_memory_type API to include size as well
2020-10-16 22:00:04 +00:00
Saurabh Gorecha e0caf8f57c Update in coreboot_get_memory_type API to include size as well
Change-Id: I3f563cffd58b0591b433c85c0ff6b71e486eb2c8
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
2020-10-16 02:23:35 +05:30
Mark Dykes dfe577a817 Merge "Don't return error information from console_flush" into integration 2020-10-14 18:59:27 +00:00
Jimmy Brisson d7b5f40823 Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:

    bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
    The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
    0x3c0U" (32 bits) is less that the right hand operand
    "18446744073709547519ULL" (64 bits).

This also resolves MISRA defects such as:

    bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
    In the expression "3U << 20", shifting more than 7 bits, the number
    of bits in the essential type of the left expression, "3U", is
    not allowed.

Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.

This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,

    92407e73        and     x19, x19, #0xffffffff

from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.

The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.

Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-10-12 10:55:03 -05:00
Jimmy Brisson 831b0e9824 Don't return error information from console_flush
And from crash_console_flush.

We ignore the error information return by console_flush in _every_
place where we call it, and casting the return type to void does not
work around the MISRA violation that this causes. Instead, we collect
the error information from the driver (to avoid changing that API), and
don't return it to the caller.

Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-10-09 10:21:50 -05:00
johpow01 35c75377a0 Workaround for Cortex A77 erratum 1925769
Cortex A77 erratum 1925769 is a Cat B erratum, present in older
revisions of the Cortex A77 processor core.  The workaround is to
set bit 8 in the ECTLR_EL1 register, there is a small performance cost
(<0.5%) for setting this bit.

SDEN can be found here:
https://documentation-service.arm.com/static/5f7c35d0d3be967f7be46d33

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I9cf0e0b5dc1e3e32e24279d2632c759cc7bd7ce9
2020-10-07 21:15:38 +00:00
Madhukar Pappireddy a4fdb893a8 Merge changes from topics "rename-herculesae-a78ae", "rename-zeus-v1" into integration
* changes:
  Rename Neoverse Zeus to Neoverse V1
  Rename Cortex Hercules AE to Cortex 78 AE
2020-10-06 23:35:55 +00:00
Madhukar Pappireddy f8dee97bab Merge "Workaround for Cortex A76 erratum 1868343" into integration 2020-10-05 22:49:10 +00:00
Jimmy Brisson 467937b63d Rename Neoverse Zeus to Neoverse V1
Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-10-05 15:14:11 -05:00
Jimmy Brisson 5effe0beba Rename Cortex Hercules AE to Cortex 78 AE
Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-10-05 15:14:11 -05:00
johpow01 55ff05f384 Workaround for Cortex A76 erratum 1868343
Cortex A76 erratum 1868343 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core.  The workaround is to
set a bit in the CPUACTLR_EL1 system register, which delays instruction
fetch after branch misprediction. This workaround will have a small
impact on performance.

This workaround is the same as workarounds for errata 1262606 and
1275112, so all 3 have been combined into one function call.

SDEN can be found here:
https://documentation-service.arm.com/static/5f2bed6d60a93e65927bc8e7

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7f2f9965f495540a1f84bb7dcc28aff45d6cee5d
2020-10-03 12:58:53 +00:00
Andre Przywara 3b456661e9 libfdt: Upgrade libfdt source files
Update the libfdt source files, the upstream commit is 73e0f143b73d
("libfdt: fdt_strerror(): Fix comparison warning").

This brings us the fixes for the signed/unsigned comparison warnings,
so platforms can enable -Wsign-compare now.

Change-Id: I303d891c82ffea0acefdde27289339db5ac5a289
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-10-02 12:15:48 +00:00
Madhukar Pappireddy c36aa3cfa5 Merge "Workaround for Cortex A77 erratum 1508412" into integration 2020-09-29 18:43:00 +00:00
Manish Pandey 609115a627 Merge changes I1ecbe5a1,Ib5945c37,Ic6b79648 into integration
* changes:
  plat/arm: Add platform support for Morello
  fdts: add device tree sources for morello platform
  lib/cpus: add support for Morello Rainier CPUs
2020-09-29 12:17:21 +00:00
André Przywara 478fc4f238 Merge "arm_fpga: Add support for unknown MPIDs" into integration 2020-09-28 18:25:03 +00:00
Manoj Kumar 2b357c3159 lib/cpus: add support for Morello Rainier CPUs
This patch adds CPU support for the Rainier CPU which is
derived from Neoverse N1 r4p0 CPU and implements the
Morello capability architecture.

Change-Id: Ic6b796481da5a66504ecb0648879446edf4c69fb
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
2020-09-28 19:33:24 +05:30
laurenw-arm aa3efe3df8 Workaround for Cortex A77 erratum 1508412
Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based on A77 revision.

This errata is explained in this SDEN:
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
2020-09-25 15:41:56 -05:00
Javier Almansa Sobrino 1994e56221 arm_fpga: Add support for unknown MPIDs
This patch allows the system to fallback to a default CPU library
in case the MPID does not match with any of the supported ones.

This feature can be enabled by setting SUPPORT_UNKNOWN_MPID build
option to 1 (enabled by default only on arm_fpga platform).

This feature can be very dangerous on a production image and
therefore it MUST be disabled for Release images.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I0df7ef2b012d7d60a4fd5de44dea1fbbb46881ba
2020-09-25 15:45:50 +01:00
Olivier Deprez 21023273c9 Merge "plat/arm: Introduce and use libc_asm.mk makefile" into integration 2020-09-24 14:39:24 +00:00
Madhukar Pappireddy 374eef025f libc: Import strtok_r from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
Made small changes to fit into TF-A project

Change-Id: I991f653a7ace04f9c84bcda78ad8d7114ea18e93
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-09-18 11:58:41 -05:00
Madhukar Pappireddy 8f5426cc4b Merge "SPE: Fix feature detection" into integration 2020-09-15 21:21:24 +00:00
Manish V Badarkhe 28e9a55fc8 lib: fconf: Implement a parser to populate CoT
Implemented a parser which populates the properties of
the CoT descriptors as per the binding document [1].
'COT_DESC_IN_DTB' build option is disabled by default and can
be enabled in future for all Arm platforms by making necessary
changes in the memory map.
Currently, this parser is tested only for FVP platform.

[1]:
https://trustedfirmware-a.readthedocs.io/en/latest/components/cot-binding.html

Change-Id: I2f911206087a1a2942aa728de151d2ac269d27cc
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-09-15 16:13:26 +01:00
Andre Przywara b85359296c SPE: Fix feature detection
Currently the feature test for the SPE extension requires the feature
bits in the ID_AA64DFR0 register to read exactly 0b0001.
However the architecture guarantees that any values greater than 0
indicate the presence of a feature, which is what we are after in
our spe_supported() function.

Change the comparison to include all values greater than 0.

This fixes SPE support in non-secure world on implementations which
include the Scalable Vector Extension (SVE), for instance on Zeus cores.

Change-Id: If6cbd1b72d6abb8a303e2c0a7839d508f071cdbe
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-09-14 18:00:18 +01:00
Mark Dykes 34029d01c6 Merge "libc: Import strlcat from FreeBSD project" into integration 2020-09-11 18:44:19 +00:00
Mark Dykes ddf04313dc Merge "libc: Add support for vsnprintf()" into integration 2020-09-11 18:42:23 +00:00
Madhukar Pappireddy 77648689ad libc: Add support for vsnprintf()
It uses the existing implementation of snprintf() function

Change-Id: Ie59418564c2e415222e819cf322c34e9a4d1f336
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-09-11 11:34:01 -05:00
Madhukar Pappireddy 238db174b5 Merge "Workaround for Neoverse N1 erratum 1868343" into integration 2020-09-11 14:56:35 +00:00
johpow01 61f0ffc40a Workaround for Neoverse N1 erratum 1868343
Neoverse N1 erratum 1868343 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core.  The workaround is to
set a bit in the CPUACTLR_EL1 system register, which delays instruction
fetch after branch misprediction. This workaround will have a small
impact on performance.

SDEN can be found here:
https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844
2020-09-10 12:32:09 -05:00
Madhukar Pappireddy 1123a5e2f9 libc: Import strlcat from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
Made small changes to fit into TF-A project

Change-Id: I07fd7fe1037857f6b299c35367c104fb51fa5cfa
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-09-09 13:48:04 -05:00
Mark Dykes 0b96df769f Merge "libc: memset: improve performance by avoiding single byte writes" into integration 2020-09-09 18:36:08 +00:00
Andre Przywara 75fab6496e libc: memset: improve performance by avoiding single byte writes
Currently our memset() implementation is safe, but slow. The main reason
for that seems to be the single byte writes that it issues, which can
show horrible performance, depending on the implementation of the
load/store subsystem.

Improve the algorithm by trying to issue 64-bit writes. As this only
works with aligned pointers, have a head and a tail section which
covers unaligned pointers, and leave the bulk of the work to the middle
section that does use 64-bit writes.

Put through some unit tests, which exercise all combinations of nasty
input parameters (pointers with various alignments, various odd and even
sizes, corner cases of content to write (-1, 256)).

Change-Id: I28ddd3d388cc4989030f1a70447581985368d5bb
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-09-03 23:00:24 +01:00
Manish Pandey 7ef3e0b31b Merge "lib: cpu: Check SCU presence in DSU before accessing DSU registers" into integration 2020-09-03 21:16:17 +00:00
Sandeep Tripathy 2274490945 psci: utility api to invoke stop for other cores
The API can be used to invoke a 'stop_func' callback for all
other cores from any initiating core. Optionally it can also
wait for other cores to power down. There may be various use
of such API by platform. Ex: Platform may use this to power
down all other cores from a crashed core.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Change-Id: I4f9dc8a38d419f299c021535d5f1bcc6883106f9
2020-09-03 09:29:22 +00:00
Alexei Fedorov e3f2b1a932 plat/arm: Introduce and use libc_asm.mk makefile
Trace analysis of FVP_Base_AEMv8A 0.0/6063 model
running in Aarch32 mode with the build options
listed below:
TRUSTED_BOARD_BOOT=1 GENERATE_COT=1
ARM_ROTPK_LOCATION=devel_ecdsa KEY_ALG=ecdsa
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
shows that when auth_signature() gets called
71.99% of CPU execution time is spent in memset() function
written in C using single byte write operations,
see lib\libc\memset.c.
This patch introduces new libc_asm.mk makefile which
replaces C memset() implementation with assembler
version giving the following results:
- for Aarch32 in auth_signature() call memset() CPU time
reduced to 20.56%.
The number of CPU instructions (Inst) executed during
TF-A boot stage before start of BL33 in RELEASE builds
for different versions is presented in the tables below,
where:
- C TF-A: existing TF-A C code;
- C musl: "lightweight code" C "implementation of the
  standard library for Linux-based systems"
https://git.musl-libc.org/cgit/musl/tree/src/string/memset.c
- Asm Opt: assemler version from "Arm Optimized Routines"
  project
https://github.com/ARM-software/optimized-routines/blob/
master/string/arm/memset.S
- Asm Linux: assembler version from Linux kernel
https://github.com/torvalds/linux/blob/master/arch/arm/lib/memset.S
- Asm TF-A: assembler version from this patch

Aarch32:
+-----------+------+------+--------------+----------+
| Variant   | Set  | Size |    Inst 	 |  Ratio   |
+-----------+------+------+--------------+----------+
| C TF-A    | T32  | 16   | 2122110003   | 1.000000 |
| C musl    | T32  | 156  | 1643917668   | 0.774662 |
| Asm Opt   | T32  | 84   | 1604810003   | 0.756233 |
| Asm Linux | A32  | 168  | 1566255018   | 0.738065 |
| Asm TF-A  | A32  | 160  | 1525865101   | 0.719032 |
+-----------+------+------+--------------+----------+

AArch64:
+-----------+------+------------+----------+
| Variant   | Size |    Inst    |  Ratio   |
+-----------+------+------------+----------+
| C TF-A    | 28   | 2732497518 | 1.000000 |
| C musl    | 212  | 1802999999 | 0.659836 |
| Asm TF-A  | 140  | 1680260003 | 0.614917 |
+-----------+------+------------+----------+

This patch modifies 'plat\arm\common\arm_common.mk'
by overriding libc.mk makefile with libc_asm.mk and
does not effect other platforms.

Change-Id: Ie89dd0b74ba1079420733a0d76b7366ad0157c2e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-09-02 16:21:34 +00:00