The register at offset 0x23 is called Digital Loopback Enable, but the
constant is COMPHY_LOOPBACK_REG0, as if there were some LOOPBACK_REG1
register or something, which there is not.
Rename the constant to COMPHY_DIG_LOOPBACK_EN.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ie88bdd864e2c9ab7e8de70ed7f3a13ee8f08ff79
Currently reg_set() and reg_set16() are implemented via
mmio_clrsetbits_32(), meaning that first bits from mask are cleared,
then data bits are set.
But these function are used everywhere according to update semantics,
where only those bits that are in mask are allowed to be changed.
Example from phy-comphy-cp110.c
mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
/* Set PHY datapath width mode for V0 */
mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
/* Set Data bus width USB mode for V0 */
mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
/* Set CORE_CLK output frequency for 250Mhz */
mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
Change the implementation to update semantics by anding data with mask.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ic72a8f64916274e08baef0b3f4c44a4fa07c1a6c
Currently reg_set() and reg_set16() are almost everywhere (both in
phy-comphy-3700.c and phy-comphy-cp110.c) used as if the semantics were
that of register update function (only bits that are set in mask are
updated):
reg_set(addr, data, mask) {
*addr = (*addr & ~mask) | (data & mask);
}
This comes both from names of arguments (data and mask), and from usage.
But both functions are in fact implemented via mmio_clrsetbits_32(), so
they actually first clear bits from mask and then set bits from data:
reg_set(addr, data, mask) {
*addr = (*addr & ~mask) | data;
}
There are only two places where this is leveraged (where some bits are
put into data argument but they are not put into the mask argument).
Fix those two usages to allow to convert the implementation from
clrsetbits semantics to update semantics.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ib29a1dd7edcdee7a39c4752dbc9dfcd600d8cb5c
The comments about selector register values are wrong.
Bit 0 configures only lane 1, bit 4 only lane 0, and bit 8 lanes 0 and
2.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Iffe42374f92654ebe570557e0d462204439cfa31
Fix comment about COMPHY status register. PCIe/GbE0 PHY is on lane 1,
while USB3/GbE1 on lane 0.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I24734a61727d56f6eab2ed1c366d7a1810dbe19d
The current definitions of reference clock speed register values
#define PCIE_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
#define USB3_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
is ambiguous. The name of the constant implies 25 MHz, but the value
implies 30 MHz, which may make the reader think that the setting has
something to do with both values.
In reality, the values have different tables for SerDes and PCIe/USB3
PHY mode. The value for 25 MHz for PCIe/USB3 mode (0x2) is the value
for 30 MHz for SerDes mode.
Instead of defining the PCIe/USB3 constants relative to SerDes
constants, define them with absolute values, thus making it a little bit
more obvious that different modes have different value tables.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I50c66c6bbe22b9a9bec4685600cb8560524a643c
The MODE_REFDIV constant is only used as mask of the MODE_REFDIV
register, but we already have MODE_REFDIV_MASK constant for that.
Drop MODE_REFDIV.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Icabb32189a7ca1a857dcf86cf0846bd0335f75d0
Constants SD_SPEED_1_25_G and SD_SPEED_2_5_G refer to SerDes frequency,
which is 1.25x that of data rate, since 1000base-x and 2500base-x use
the 8b/10b encoding:
mode frequency data rate
1000base-x 1.25 GHz 1 Gbps
2500base-x 3.125 GHz 2.5 Gbps
But the first constant refers to the frequency, while the second to the
data rate, which does not make sense.
Since the values in the specification refer to frequency, change the
name of the constant SD_SPEED_2_5_G to SD_SPEED_3_125_G to also refer to
the frequency, as SD_SPEED_1_25_G does.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I7670b45fa685aff93b3cafd84cf30d93620d8da1
According to Functional Specification, the common PHY register at offset
0x3f is actually Generation 3 Setting 2, while the register at offset
0x112 is Generation 2 Setting 3.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I4626672cbee2d08da1da7839a3cf3f90e78fa101
According to Functional Specification, the register at bit 1 of PHY
Configuration 1 is called PIN_PU_IVREF, not PIN_PU_IVEREF. Fix this.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I912fa4a1956bf0b1b35a24925db03e3dbbe1adf3
When tf-a is built with the llvm toolchain, the compiler optimizes the
variable in some way which results in SCMI_MSG_GET_TOKEN assert failure
in multiple places. This patch makes the msg_header variable in
mailbox_mem struct volatile, which seems to fix the issue.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I1d28b30a6472fc23ed85adff9cf73dfb536e39cc
It doesn't look correct to use mbed TLS defines directly in the Event
Log driver as this driver may use another Crypto library in future.
Hence mbed TLS Crypto dependency on Event Log driver is removed by
introducing generic Crypto defines and uses those in the Event Log
driver to call Crypto functions.
Also, updated mbed TLS glue layer to map these generic Crypto defines
to mbed TLS library defines.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ibc9c751f60cbce4d3f3cf049b7c53b3d05cc6735
As mpidr is unsigned long long, U should be ULL. We use macro to
fix this issue.
Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: I7dfd51a63f27f471794bcbf72ffff0c1a0598b46
Add a UART/USART driver for STM32 with complete a hardware support;
it used for STM32CubeProgrammer support with even parity.
This driver is not used for console, which is already handle
by a simple driver (drivers/st/uart/aarch32/stm32_console.S).
Change-Id: Ia9266e5d177fe7fd09c8a15b81da1a05b1bc8b2d
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
The PLL4 can be used by ROM code as the source clock of USB PHYC and,
in this case, the PLL4 configuration must be preserved
with pll4_preserve to avoid USB disturbance.
This patch also adds an error when the clock tree PLL4 configuration
is not the PLL4 configuration used by ROM code; this error allows to
detect a invalid clock tree.
This commit corrects the coverity issue 343023.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I4bae9312a2db8dd342a38e649513d689b13976bb
Sometimes when changing UART clock from TBG to XTAL, UART HW enters into
some broken state. It does not transit characters from TX FIFO anymore
and TX FIFO stays always empty. TX FIFO reset does not recover UART HW
from this broken state.
Experiments show that external reset can fix UART HW from this broken
state.
TF-A fatal error handler calls console_a3700_core_init() function to
initialize UART HW. This handler may be called anytime during CPU
runtime, also when kernel is running.
U-Boot or Linux kernel may change UART clock to TBG to achieve higher
baudrates. During initialization, console_a3700_core_init() resets UART
configuration to default settings, which means that it also changes
UART clock from TBG to XTAL.
Do an external reset of UART via North Bridge Peripheral reset register
to prevent this UART hangup.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8990bce24d1a6fd8ccc47a2cd0a5ff932fcfcf14
If TX FIFO is not empty, do not touch UART settings and let UART HW
transmit remaining bytes from TX FIFO. New UART settings are then set
only after TX FIFO is reset.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2976c0a4fbb841d3a79d42ef67c06e70174afc3b
Followup changes will need function arguments in registers x0, x1 and
x2. Do not modify x1 and x2 registers and instead use scratch x3 and x4
registers for storing local variables.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8551a802995f39128d2f4a8f8076b5bf463d0db0
Renamed a macro 'INVALID_ID' to 'EVLOG_INVALID_ID' to avoid its clash
with other macro names and to show it is explicitly used for Event
Log driver.
Change-Id: Ie4c92b3cd1366d9a59cd6f43221e24734865f427
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
The previous codes were using the cntpct_el0 to check the time
elapsed. But this physical timer does not seem to count for
the expected time resulting in gic fmu communication failures
on Tegra platforms.
This patch uses the delay_timer instead to use a platform
defined timer for calculating timeouts.
Change-Id: Ic8646ad1662c9928ac64c4152deb27e8c86fe344
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
sha 4ce3e99a3 introduced printf format specifiers for fixed width
types, which uses PRI*64 instead of "ll" for 64 bit values.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ic6811cc1788c698adde0807e5f8ab5290a900a26
Use long instead of long long on aarch64 for 64_t stdint types.
Introduce inttypes.h to properly support printf format specifiers for
fixed width types for such change.
Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
* changes:
feat(arm_fpga): write UART baud base clock frequency into DTB
feat(arm_fpga): query PL011 to learn system frequency
refactor(arm_fpga): move command line code into separate function
fix(fdt): avoid output on missing DT property
feat(arm_fpga): add ITS autodetection
feat(arm_fpga): determine GICR base by probing
feat(gicv3): introduce GIC component identification
feat(libfdt): also allow changing base address
fix(arm_fpga): avoid re-linking from executable ELF file
Correctly handle USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION request
in USB driver and support a different result than
USB_DESC_TYPE_CONFIGURATION with the new optional ops
get_other_speed_config_desc().
The support of this descriptor is optionnal and is only
required when high-speed capable device which can operate at its
other possible speed.
This patch allows to remove the pbuf update in usb_core_get_desc()
and solves an issue on USB re-enumeration on STM32MP15 platform
as the result of get_config_desc() is a const array.
This issue is not see on normal use-case, as the USB enumeration
is only done in ROM code and TF-A reuse the same USB descritors.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I8edcc1e45065ab4e45d48f4bc37b49120674fdb0
Remove the unnecessary cast on the result of function which
already return the correct type.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie21f7e78a880d30d1f31e32b3d2c3fb09489d65b
The GIC specification describes ID registers in each GIC register frame
(PIDRx), which can be used to identify a GIC component. The Arm Ltd. GIC
implementations use certain ID values to identify the distributor, the
redistributors and other parts like ITSes.
Introduce a function that reads those part number IDs, which are spread
over two registers. The actual numbers are only meaningful in connection
with a certain GIC model, which would need to be checked beforehand, by
the caller.
Change-Id: Ia6ff326a1e8b12664e4637bc8e2683d2b5c7721c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
CID 373791: Control flow issues (DEADCODE)
CID 373789: Control flow issues (DEADCODE)
Since USBD_EP_NB = 1 for DFU stack on STMP32MP15 platform (only EP0 is
required for DFU support) the value of num can't be different of 0
and the code can't be reached in usb_core_receive / usb_core_transmit.
Add a simple sub-function with this part of code.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I07a56909bb1e6de19ce52da7945b6d2916be8538
Correct the invalid test on NULL pointer pdev->class in
usb_core_set_config function.
This patch fix the coverity errors:
** CID 373790: Null pointer dereferences (FORWARD_NULL)
/drivers/usb/usb_device.c: 182 in usb_core_set_config()
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I83e43261bafa2d47f800e56df0b047a6c58a1e29
Add a device driver for Synopsis DWC2 USB IP of STM32MP15x,
this USB OTG device is only supported in device mode.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I90b21f094f6637b85f3ace23a3a3a2f6fd4e0951
Add a new USB framework to manage an USB device profile (USBD)
based on a peripheral controller driver (PCD).
This USB stack can be use to implement any Universal Serial Bus Device
Class in TF-A on top of a USB driver defined in the platform.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I7971ec6d952edec3511157a198e6e5359df4346b
there are features which are marked as experimental even though they
are stable and used for quite some time.
Following features are no longer marked as experimental
- SPMD
- MEASURED_BOOT
- FCONF and associated build flags
- DECRYPTION_SUPPORT and associated build flags
- ENABLE_PAUTH
- ENABLE_BTI
- USE_SPINLOCK_CAS
- GICv3 Multichip support
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I4bb653d9c413c66095ec31f0b8aefeb13ea04ee9
Currently the SCMI driver reports:
INFO: Initializing driver on Channel 0
on the console, which is not very specific (which driver?).
Add "SCMI" to the message so the user knows what the firmware is trying
to initialise.
Change-Id: Id8202655d07b8e12fe07670d462c6202e6eae2f0
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* changes:
feat(plat/rcar): change process for Suspend To RAM
fix(plat/rcar): change process that copy code to system ram
fix(plat/rcar): fix cache maintenance process of reading cert header
fix(plat/rcar): fix to load image when option BL2_DCACHE_ENABLE is enabled
Change processing of invalidate instruction cache to after changing
the RAM attribute.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # squash with rcar_gen3: drivers: Disable data cache while Suspend To RAM
Change-Id: I61339fc5415b26074b1e0753da4c4a432e8f83d9
- Modify load destination variable of the Cert Header to static.
- Modify the return value to error (IO_FAIL) when failed to check
the Cert Header.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ief09a841ec8d2ae236de82d04855e6a47cfb43f0
This change aims to make the UFS code more robust by performing a
controller reset if linkstartup fails. This idea was borrowed from
Linux's ufshcd_link_startup function.
Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: I6b52148d1bf155b11198dc82a39b1120057adaaf
This change aims to make the UFS code more robust by adding retry logic
and timeouts to ufshc_reset. We also define a new function
ufshc_hce_enable for Host Controller Enable (HCE). The inner and outer
retry pattern is based on Linux's ufshcd_hba_execute_hce function.
Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: I9403a5a25d3ca50af5f2f9a65b774f6a2d7a9626
This change aims to make the UFS code more robust by removing asserts
and adding retry logic. We also reduce repetition by reusing
ufshc_send_uic_cmd for DME_GET and DME_SET commands.
Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: Id70aa1687d5ca78dc7d47234372255ac5a04a612
Fixed a below build failure with CC-713 library
error:
implicit declaration of function ‘mbedtls_x509_get_rsassa_pss_params’
[-Werror=implicit-function-declaration]
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: If298ec16d133cf54413c299327b2c007ec4117b2
* changes:
fix(stpmic1): fix power switches activation
fix(stpmic1): update error cases return
refactor(stpmic1): use BIT and GENMASK helpers
fix(stm32mp1_clk): keep RTC clock always on
fix(stm32mp1_clk): set other clocks as always on
It looks safer and cleaner approach to record the measurement taken by
BL1 straightaway in TCG Event Log instead of deferring these recordings
to BL2.
Hence pull in the full-fledged measured boot driver into BL1 that
replaces the former ad-hoc platform interfaces i.e.
bl1_plat_set_bl2_hash, bl2_plat_get_hash.
As a result of this change the BL1 of Arm FVP platform now do the
measurements and recordings of below images:
1. FW_CONFIG
2. TB_FW_CONFIG
3. BL2
Change-Id: I798c20336308b5e91b547da4f8ed57c24d490731
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Currently, the Event Log driver does platform layer work by invoking
a few platform functions in the 'event_log_finalise' call. Doing
platform work does not seem to be the driver's responsibility, hence
moved 'event_log_finalise' function's implementation to the platform
layer.
Alongside, introduced few Event Log driver functions and done
some cosmetic changes.
Change-Id: I486160e17e5b0677c734fd202af7ccd85476a551
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Right now, event_log_init() does 2 things:
1) It writes all the necessary TCG data structures in the event log buffer.
2) It writes the first measurement (BL2's).
Step 2) introduces in the TCG event log driver an assumption on what
is getting measured and in what order. Ideally, the driver should only
be concerned about generic operations, such as initializing the event
log or recording a measurement in it. As much as possible, we should
design the driver such that it could be reused in another project that
has a different measure boot flow.
For these reasons, move step 2) up to the caller, plat_mboot_init() in
this case. Make event_log_record() a public function for this purpose.
This refactoring will also help when we make BL1 record BL2's
measurement into the event log (instead of BL2). Both BL1 and BL2 will
need to call the driver's init function but only BL1 will need
recording BL2's measurement. We can handle this through different
implementations of plat_mboot_init() for BL1 and BL2, leaving the TCG
event log driver unchanged.
Change-Id: I358e097c1eedb54f82b866548dfc6bcade83d519
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
To a layman in TCG linguo, add_event2() is not straight forward to
understand. Rename the function into event_log_record().
Change-Id: I75d53a656425cd78a41ebf2c4c4e4e57687adc0d
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
With the removal of the generic functions measured_boot_init()/finish(),
measured_boot.mk becomes specific to the TCG event log backend. Change
its file name to event_log.mk.
Also, the Event Log driver is one of the backend of measured boot hence
created a separate folder for it under the measured_boot directory.
Alongside done some cosmetic changes (adding a comment and fixing
identation).
Change-Id: I4ce3300e6958728dc15ca5cced09eaa01510606c
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Right now, the measured boot driver is strongly coupled with the TCG
event log driver. It would not be possible to push the measurements
somewhere else, for instance to a physical TPM.
To enable this latter use case, turn the driver's init and teardown
functions into platform hooks. Call them bl2_plat_mboot_init()/finish().
This allows each platform to implement them appropriately, depending on
the type of measured boot backend they use. For example, on a platform
with a physical TPM, the plat_mboot_init() hook would startup the TPM
and setup it underlying bus (e.g. SPI).
Move the current implementation of the init and teardown function to the
FVP platform layer.
Finally move the conditional compilation logic (#if MEASURED_BOOT) out
of bl2_main() to improve its readability. Provide a dummy implementation
in the case measured boot is not included in the build.
Change-Id: Ib6474cb5a9c1e3d4a30c7f228431b22d1a6e85e3
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
tpm_record_measurement() function name suggests that:
- It only records a measurement but does not compute it.
This is not the case, the function does both.
- It stores this measurement into a TPM (discrete chip or fTPM).
This is not the case either, the measurement is just stored into
the event log, which is a data structure hold in memory, there is
no TPM involvement here.
To better convey the intent of the function, rename it into
event_log_measure_and_record().
Change-Id: I0102eeda477d6c6761151ac96759b31b6997e9fb
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
The mvebu_a3700_comphy_pcie_power_on() function does not configure the
PHY selector explicitly, it relies on the register default value.
Configure the PHY selector just in case someone changed the default
value.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I54048b4bb7a5eced36f7fe6592ebe108f978fff0
Fix compile warning that ‘mask’ may be used uninitialized.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I75a443dbc36d7bd174fe317616fd95cd096306fc
Add enable bit mask description because power switches
are not all enabled by bit 0.
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: If7c9ae7d800adee8e25416ca35db1be20452741f
Use errno values, or the return of called functions, instead of -1.
Correct some MISRA issues, like braces.
Change-Id: If7b53de5cbfb4d2c9979bce0e594dd92bf07a77a
Signed-off-by: Yann Gautier <yann.gautier@st.com>
On battery powered systems the RTC keeps the date/time across
system reboot.
The RTC clock should not be disabled otherwise the date/time
counter gets stopped.
Tag RTC clock as always on.
Signed-off-by: HE Shushan <shushan.he@st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Change-Id: I6455c3c740d2e5add28255eb84f8ebaf2870d9d8
MPUDIV dividers are stored in a constant array, under bit shifts form.
They must be used in this way by the clock driver.
Change-Id: If758f7a4048eff956067a10a42ab0983a20a000d
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Correct MCU clock parent selector: MCU subsystem clock is derived
from clock PLL3_P, not PLL3.
Correct AXI clock parent selector: AXI subsystem clock is derived
from clock PLL2_P, not PLL2.
This change also renames MCU clock and AXI clock resources to
prevent confusion.
Change-Id: If55618d180e7dce8e4f0977b0e586a6fa8ef28d1
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
To avoid parsing device tree file too often, keep the RCC node
offset value in a variable in fdt_get_rcc_node().
Change-Id: Ibb23ff92247d57c65a23517b8f3473f639794d2a
Signed-off-by: Yann Gautier <yann.gautier@st.com>
AXI, MPU and MCU clocks are always on, put them in the list
in the function clock_is_always_on().
Change-Id: I969a442274d2da6c59636f3293de1c31b4c8e3b1
Signed-off-by: Yann Gautier <yann.gautier@st.com>
* changes:
feat(plat/rcar3): keep RWDT enabled
feat(drivers/rcar3): add extra offset if booting B-side
feat(plat/rcar3): modify LifeC register setting for R-Car D3
feat(plat/rcar3): modify SWDT counter setting for R-Car D3
feat(plat/rcar3): update DDR setting for R-Car D3
feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3
feat(plat/rcar3): add process of SSCG setting for R-Car D3
feat(plat/rcar3): add process to back up X6 and X7 register's value
feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR
feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up
feat(plat/rcar3): change the memory map for OP-TEE
feat(plat/rcar3): use PRR cut to determine DRAM size on M3
feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537
fix(plat/rcar3): fix disabling MFIS write protection for R-Car D3
fix(plat/rcar3): fix eMMC boot support for R-Car D3
fix(plat/rcar3): fix version judgment for R-Car D3
fix(plat/rcar3): fix source file to make about GICv2
fix(drivers/rcar3): console: fix a return value of console_rcar_init
* changes:
fix(drivers/marvell/comphy-cp110): fix error code in pcie power on
fix(drivers/marvell/comphy-3700): handle failures in power functions
fix(drivers/marvell/comphy-3700): fix address overflow
refactor(drivers/marvell/comphy-3700): simplify usage of comphy_sgmii_phy_init()
refactor(drivers/marvell/comphy-3700): simplify usage of indirect access on lane2
refactor(drivers/marvell/comphy-3700): simplify usage of sata power off
Add support for Arm Ethos-N NPU multi-device.
The device tree parsing currently only supports one NPU device with
multiple cores. To be able to support multi-device NPU configurations
this patch adds support for having multiple NPU devices in the device
tree.
To be able to support multiple NPU devices in the SMC API, it has been
changed in an incompatible way so the API version has been bumped.
Signed-off-by: Laurent Carlier <laurent.carlier@arm.com>
Change-Id: Ide279ce949bd06e8939268b9601c267e45f3edc3
Adding load, authentication, and transfer functionality from FVP R BL1 to
BL33, which will be the partner runtime code.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I293cad09739dacac0d20dd57c1d98178dbe84d40
Function polling_with_timeout() returns last value from polled register
on failure and zero on success. So set "ret" variable to error code
-ETIMEDOUT on error like it is done in other functions.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I16cac81bbcbe2113e139722dc0e8fc2b85428d1b
Subroutines in power functions may fail. So propagate failures from
subroutines back to the caller of power function with appropriate error
code in return value.
Function polling_with_timeout() returns last value from polled register
on failure and zero on success. So return -ETIMEDOUT on error from power
functions like it is doing Marvell comphy-cp110 driver.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6c709c0c9616ab26829616a42a85b713f314b201
Physical address has to be stored in 64-bit data type as Armada 3720 is
64-bit platform. Driver already uses uintptr_t type for this purpise.
Change type of 'offset' variables in mvebu_a3700_comphy_usb3_power_on()
and mvebu_a3700_comphy_sgmii_power_on() / off() functions to uintptr_t
as in this variable is stored physical address of registers.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I69581714f8899d21cc1a27005747708f0f1cd933
Parameter 'comphy_index' is not used and parameter 'mode' is used only
to check if speed is 1 Gbps or not.
Remove parameter 'comphy_index' and instead of 32-bit variable 'mode',
pass only boolean value which represents 1 Gbps speed.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I018d158f689ddf7d1f57003717d709c00d988fba
For code cleanup add two helper functions comphy_sata_set_indirect() and
comphy_usb_set_indirect() for SATA and USB 3.0 modes and remove additional
'mode' argument which is not needed anymore.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I23146f569db318dbaed5d411d7d175abf6efff85
Function mvebu_a3700_comphy_sata_power_off() uses comphy_mode parameter
only for extracting mode bits. Mode is always COMPHY_SATA_MODE, so
there is no need to pass comphy_mode parameter to this function. Use
directly COMPHY_SATA_MODE in mvebu_a3700_comphy_sata_power_off().
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ib6b7c2bf62c1ef4d8a6af240c08696d5cd506b14
Change the fdt_get_rcc_node function to static, as it is used only in
stm32mp_clkfunc.c file; it is only a cleanup change without functional
modification.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ib4ef110f6f1b16dbaa727a065e40275d3cf58a73
In BL32, only skip UART initialization if UART enable bit is set.
Due to patch [1], a reset of UART is done in crash console init.
In this case, UART should then be reconfigured.
[1] 7fa2e96e1 ("stm32mp1: add UART reset in crash console init")
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I650d4c387b60dd74b780e6f3adfd629ea44f5834
The file is first generated with the peripheral spirit XML file.
And then we add some common definition, to ease driver development.
Change-Id: I4c222cf006caf27cda6da044eaf184ce66bb1442
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Further information such as boot instance are sent over backup
registers. In order to guarantee direct access to backup registers
in uboot, we will keep the RTC clock enabled.
Change-Id: I16572d422bfebbf39190a87db8046df486ce91c8
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
When RTC clock source is HSE, the RTCDIV is not taken into account.
Change-Id: I1613b638e8932c03f3349adb01e13f5294a3bf5d
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
The clksrc value contains the RCC register address and the clock
source number. When applying the clock source, we should filter out
the RCC register address from the given value.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4345b03de7b9afd1df78df4131431cf1eb43ec17
On most of SPI NAND, the read id command needs a dummy byte,
except GIGADEVICE SPI NAND that needs an address.
To be compliant with all memories providers, the first byte returns
by the READ_ID command is not relevant (garbage).
Change-Id: Ife74ccab333dd1a04799abe230d3f07fa6ea1edb
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
This patch checks that the SPI NAND parameters needed by
the framework have been set before starting to read data.
Change-Id: I17b36606701c44864dcf1783f810da5c8cbf88f2
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Disabling filter 0 causes inability to access DRAM.
An attempt leads to an abort.
ARM manual disallows to disable filter 0, but if we do
that from SRAM, nothing bad happens.
This patch prevents disabling of a filter 0, allowing to
reconfigure other filters from DRAM.
Note: this patch doesn't change the logic after reset.
It is only needed in case someone wants to reconfigure the
previously configured TZASC.
Change-Id: I196a0cb110a89afbde97f64a94df3101f28708a4
Signed-off-by: stsp@users.sourceforge.net
In case MFISBTSTSR bit 4 is 1, that means the loader was started as
B-side. Load the remaining boot components from 8 MiB offset.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I11d882f30ca4f0cf55fd28d3470ff1063d350d10
- Added the condition where output the SSCG (MD12) setting
to log for R-Car D3.
- Added the process to switching the bit rate of SCIF by the
SSCG (MD12) setting value for R-Car D3.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Iaf07fa4df12dc233af0b57569ee4fa9329f670a9
Modified the operation register to clearing the state bit of
the SYSCISR register from SYSCISR to SYSCISCR.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I9a0820b6414425fa2f4197f60852137827414a4d
Added the process of SYSECEXTMASK bit set/clear for following
power Resume/Shutoff flow.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I71ed22840a42e7ab7d87bfd4241eec6f5ddb129b
Marek Behún
sah01
Manish V Badarkhe
Sandrine Bailleux
Madhukar Pappireddy
Ming Huang
Nicolas Le Bayon
Patrick Delaunay
Pali Rohár
anzhou
Manish Pandey
Scott Branden
André Przywara
Patrick Delaunay
Joanna Farley
Toshiyuki Ogasahara
Jorge Troncoso
Mark Dykes
Jiafei Pan
Pascal Paillet
Yann Gautier
HE Shushan
Yann Gautier
Gabriel Fernandez
Etienne Carriere
Laurent Carlier
laurenw-arm
Lionel Debieve
Gabriel Fernandez
Christophe Kerello
Stas Sergeev
Marek Vasut