There are additional instruction needed to enable the global timer.
This fixes the global timer initialization
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Idaf2d23359aacc417e2b7d8cdf1688b5cd17ca98
The CCU initialization loop uses the wrong units, this fixes that. This
also fixes snoop filter register set bits should be used instead of
overwriting the register
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia15eeeae5569b00ad84120182170d353ee221b31
The size of buffer currently used to store the FDT passed from U-Boot as
a platform parameter is not large enough to store some RK3399 device
trees. The largest RK3399 device tree currently in U-Boot (for the
Pinebook Pro) is about 70KB in size when passed to TF-A, so increase the
buffer size to 128K which gives some headroom for possibly larger FDTs
in future.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Change-Id: I414caf20683cd47c02ee470dfa988544f3809919
FPGAINTF wasn't enabled when configuring pinmux. This fixes the issue.
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: I5a6aacd504901b8f7327b2f4854b8a77d0c37019
DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
This fixes a few issues on the Agilex clock configuration:
- Set clock manager into boot mode before configuring clock
- Fix wrong divisor used when calculating vcocalib
- PLL sync configuration should be read and then written
- Wait PLL lock after PLL sync configuration is done
- Clear interrupt bits instead of set interrupt bits after configuration
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: I54c1dc5fe9b102e3bbc1237a92d8471173b8af70
As per "include/export/README", TF-A code should never include export
headers directly. Instead, it should include a wrapper header that
ensures the export header is included in the right manner.
"tbbr_img_def_exp.h" is directly included in TF-A code, this patch
replaces it with its wrapper header "tbbr_img_def.h".
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I31c1a42e6a7bcac4c396bb17e8548567ecd8147d
Change a topology map from internal database
to SPD based for 32bit bus width mode
Change-Id: I803166893ddc2fd916fc8a1c27fffd34b6ec0c72
Signed-off-by: Alex Leibovich <alexl@marvell.com>
Remove pll powerdown from pll configuration sequence to improve
stability. Remove redundant cases, which no longer exist.
Also get rid of irrelevant definition of CPU_2200_DDR_1200_RCLK_1200,
which is not used by 806/807.
Change-Id: If911e7dee003dfb9a42fafd7ffe34662f026fd23
Signed-off-by: Alex Leibovich <alexl@marvell.com>
This commit introduces 32-bit DDR topology map initialization.
For that purpose a new DDR32 build flag is added, with
according documentation update.
Change-Id: I169ff358c2923afd984e27bc126dc551dcaefc01
Signed-off-by: Alex Leibovich <alexl@marvell.com>
This commit introduces two changes:
- remove hardcoded references to mci0 from the driver
- perform mci optimization for all mci interfaces
It fixes performance issues observed on cn9132 CP2.
Change-Id: I4e040cd54ff95c9134035ac89b87d8feb28e9eba
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
The mci_initialize function name was misleading. The function itself
doesn't initialize MCI in general but performs MCI link tuning for
performance improvement.
Change-Id: I13094ad2235182a14984035bbe58013ebde84a7e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Snoop filter needs to be enabled once per cluster.
Change-Id: I241e72f21982142ba290c7547df6f434e6a6a98d
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
By default all external CPs start with configuration address space set to
0xf200_0000. To overcome this issue, go in the loop and initialize the
CP one by one, using temporary window configuration which allows to access
each CP and update its configuration space according to decoding
windows scheme defined for each platform.
In case of cn9130 after this procedure bellow addresses will be used:
CP0 - f2000000
CP1 - f4000000
CP2 - f6000000
When the re-configuration is done there is need to restore previous
decoding window configuration(init_io_win).
Change-Id: I1a652bfbd0bf7106930a7a4e949094dc9078a981
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
As a preparation for upcoming support for CN9130 platform, which is
classified as OcteonTx2 product but inherits functionality from a8k,
allow to use a8k_common.mk and mss_common.mk from outside of
PLAT_FAMILY_BASE.
Above is done by introducing BOARD_DIR which needs to be set by each
platform, before including a8k_common.mk and mss_common.mk. This will
allow to use mentioned mk files not only for platforms located under
previously defined PLAT_FAMILY_BASE.
Change-Id: I22356c99bc0419a40ae11e42f37acd50943ea134
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
plat, include/plat) are moved to the new "armada" sub-folder.
Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Current value is 16, count the MAP_REGION calls gets us at least 17,
so increase the max value to 20 to have a bit of a margin.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I93d0324f3d483758366e758f8f663545d365e03f
64KB was not enouth to handle fdt, bl2 shows
following error message.
"ERROR: Invalid Device Tree at 0x10000000000: error -3"
This patch increases the size to 1MB to address above error.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I0726a0cea95087175451da0dba7410acd27df808
Use ETZPC driver to configure secure aware interfaces to assign
them to non-secure world. Sp_min also configures BootROM resources
and SYSRAM to assign both to secure world only.
Define stm32mp15 SoC identifiers for the platform specific DECPROT
instances.
Change-Id: I3bec9f47b04bcba3929e4df886ddb1d5ff843089
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
BL31_CACHE_DISABLE flag was introduced as a work-around
for the older SoC revisions. Since it is not relevant in the
newest versions, toggle it to be disabled by default.
One can still specify it by adding 'BL31_CACHE_DISABLE=1'
string to the build command.
Change-Id: I11b52dade3ff7f8ee643b8078c6e447c45946570
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Core spm_mm code expects the translation tables are located in the
inner & outer WBWA & shareable memory.
REGISTER_XLAT_CONTEXT2 macro is used to specify the translation
table section in spm_mm.
In the commit 363830df1c (xlat_tables_v2: merge
REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}), REGISTER_XLAT_CONTEXT2
macro explicitly specifies the base xlat table goes into .bss by default.
This change affects the existing SynQuacer spm_mm implementation.
plat/socionext/synquacer/include/plat.ld.S linker script intends to
locate ".bss.sp_base_xlat_table" into "sp_xlat_table" section,
but this implementation is no longer available.
This patch adds the base table section name parameter for
REGISTER_XLAT_CONTEXT2 so that platform can specify the
inner & outer WBWA & shareable memory for spm_mm base xlat table.
If PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME is not defined, base xlat table
goes into .bss by default, the result is same as before.
Change-Id: Ie0e1a235e5bd4288dc376f582d6c44c5df6d31b2
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
This should allow git to easily track file moves
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Change-Id: I1592cf39a4f94209c560dc6d1a8bc1bfb21d8327
This allows to build for k3-based boards that use a different UART as
console, such as the IOT2050 which requires K3_USART=1.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I7171f86c3cabae2c575b8fbeecef839b48bd109b
Changes stm32mp1 reset driver to API to add a timeout argument
to stm32mp_reset_assert() and stm32mp_reset_deassert() and
a return value.
With a supplied timeout, the functions wait the target reset state
is reached before returning. With a timeout of zero, the functions
simply load target reset state in SoC interface and return without
waiting.
Helper functions stm32mp_reset_set() and stm32mp_reset_release()
use a zero timeout and return without a return code.
This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c
accordingly without any functional change.
functional change.
Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
The patch fixes BL31 linker script error
"Init code ends past the end of the stacks"
for platforms with number of CPUs less than 4,
which is caused by __STACKS_END__ address being
lower than __INIT_CODE_END__.
The modified BL31 linker script detects such cases
and increases the total amount of stack memory,
setting __STACKS_END__ = __INIT_CODE_END__, and
CPUs' stacks are calculated by BL31 'plat_get_my_stack'
function accordingly. For platforms with more than 4 CPUs
and __INIT_CODE_END__ < __STACKS_END__ stack memory does not
increase and allocated CPUs' stacks match the existing
implementation.
The patch removes exclusion of PSCI initialization
functions from the reclaimed .init section in
'arm_reclaim_init.ld.S' script, which increases the
size of reclaimed memory region.
Change-Id: I927773e00dd84e1ffe72f9ee534f4f2fc7b6153c
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This patch adds support for Total Compute (TC0) platform. It is an
initial port and additional features are expected to be added later.
TC0 has a SCP which brings the primary Cortex-A out of reset
which starts executing BL1. TF-A optionally authenticates the SCP
ram-fw available in FIP and makes it available for SCP to copy.
Some of the major features included and tested in this platform
port include TBBR, PSCI, MHUv2 and DVFS.
Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef
Signed-off-by: Usama Arif <usama.arif@arm.com>
Fixed build error for dualroot chain of trust.
Build error were thrown as below while compiling the code for
dualroot chain of trust:
aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o:
(.bss.auth_img_flags+0x0): multiple definition of `auth_img_flags';
./build/fvp/debug/bl1/cot.o:(.bss.auth_img_flags+0x0): first defined here
aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o:
(.rodata.cot_desc_size+0x0): multiple definition of `cot_desc_size';
./build/fvp/debug/bl1/cot.o:(.rodata.cot_desc_size+0x0): first defined here
aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o:
(.rodata.cot_desc_ptr+0x0): multiple definition of `cot_desc_ptr';
./build/fvp/debug/bl1/cot.o:(.rodata.cot_desc_ptr+0x0): first defined here
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I1a426c4e7f5f8013d71dafc176c7467c1b329757
PSCI demands that SYSTEM_OFF must not return. While it seems like a
generic ATF bug that this is possible when a platform does not Implement
a corresponding handler, let's do that here until it's addressed
differently.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I4c08948b18bbfdc3a24214f2ae0fbad9e017ada1
SPCI is renamed as PSA FF-A which stands for Platform Security
Architecture Firmware Framework for A class processors.
This patch replaces the occurrence of SPCI with PSA FF-A(in documents)
or simply FFA(in code).
Change-Id: I4ab10adb9ffeef1ff784641dfafd99f515133760
Signed-off-by: J-Alves <joao.alves@arm.com>
We query the UART base address and clk frequency in runtime
using fconf getter APIs.
Change-Id: I5f4e84953be5f384472bf90720b706d45cb86260
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
This patch introduces the populate function which leverages
a new driver to extract base address and clk frequency properties
of the uart serial node from HW_CONFIG device tree.
This patch also introduces fdt helper API fdtw_translate_address()
which helps in performing address translation.
Change-Id: I053628065ebddbde0c9cb3aa93d838619f502ee3
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
This patch enables SDEI support for all Tegra platforms, with
the following configuration settings.
* SGI 8 as the source IRQ
* Special Private Event 0
* Three private, dynamic events
* Three shared, dynamic events
* Twelve general purpose explicit events
Verified using TFTF SDEI test suite.
******************************* Summary *******************************
Test suite 'SDEI' Passed
=================================
Tests Skipped : 0
Tests Passed : 5
Tests Failed : 0
Tests Crashed : 0
Total tests : 5
=================================
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I1922069931a7876a4594e53260ee09f2e4f09390
This patch enables the v8.6 extension to add a delay before WFE traps
are taken. A weak hook plat_arm_set_twedel_scr_el3 has been added in
plat/common/aarch64/plat_common.c that disables this feature by default
but platform-specific code can override it when needed.
The only hook provided sets the TWED fields in SCR_EL3, there are similar
fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to control WFE trap delays in
lower ELs but these should be configured by code running at EL2 and/or EL1
depending on the platform configuration and is outside the scope of TF-A.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I0a9bb814205efeab693a3d0a0623e62144abba2d
Query the GICD and GICR base addresses in runtime using fconf getter
APIs.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I309fb2874f3329ddeb8677ddb53ed4c02199a1e9
CoT used for BL1 and BL2 are moved to tbbr_cot_bl1.c
and tbbr_cot_bl2.c respectively.
Common CoT used across BL1 and BL2 are moved to
tbbr_cot_common.c.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I2252ac8a6960b3431bcaafdb3ea4fb2d01b79cf5
This patch sets ENABLE_STACK_PROTECTOR=strong and implements
the platform support to generate a stack protection canary value.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ia8afe464b5645917b1c77d49305d19c7cd01866a
This patch introduces dynamic configuration for SDEI setup and is supported
when the new build flag SDEI_IN_FCONF is enabled. Instead of using C arrays
and processing the configuration at compile time, the config is moved to
dts files. It will be retrieved at runtime during SDEI init, using the fconf
layer.
Change-Id: If5c35a7517ba00a9f258d7f3e7c8c20cee169a31
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Co-authored-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Currently BL2 passes TOS_FW_CONFIG address and size through registers to
BL31. This corresponds to SPMC manifest load address and size. The SPMC
manifest is mapped in BL31 by dynamic mapping. This patch removes BL2
changes from generic code (which were enclosed by SPD=spmd) and retrieves
SPMC manifest size directly from within SPMD. The SPMC manifest load
address is still passed through a register by generic code.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I35c5abd95c616ae25677302f0b1d0c45c51c042f
As a follow-up to bdd2596d4, and related to SPM Dispatcher
EL3 component and SPM Core S-EL2/S-EL1 component: update
with cosmetic and coding rules changes. In addition:
-Add Armv8.4-SecEL2 arch detection helper.
-Add an SPMC context (on current core) get helper.
-Return more meaningful error return codes.
-Remove complexity in few spmd_smc_handler switch-cases.
-Remove unused defines and structures from spmd_private.h
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I99e642450b0dafb19d3218a2f0e2d3107e8ca3fe
This patch returns the SOC version and revision values from
the 'plat_get_soc_version' and 'plat_get_soc_revision' handlers.
Verified using TFTF SMCCC_ARCH_SOC_ID test.
<snip>
> Executing 'SMCCC_ARCH_SOC_ID test'
TEST COMPLETE Passed
SOC Rev = 0x102
SOC Ver = 0x36b0019
<snip>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibd7101619143b74f6f6660732daeac1a8bca3e44
New helper functions to get GPIO banks configuration from the FDT.
stm32_get_gpio_bank_pinctrl_node() allows stm32mp platforms to
differentiate specific GPIO banks when these are defined with a specific
path in the FDT.
fdt_get_gpio_bank_pin_count() returns the number of pins in a GPIO bank
as it depends on the SoC variant.
Change-Id: I4481774152b3c6bf35bf986f58e357c2f9c19176
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Relation between GPIO banks and their base address and offset address
if platform dependent. This change moves helper functions
stm32_get_gpio_bank_base() and stm32_get_gpio_bank_offset() from
plat/st/common to plat/st/stm32mp1/.
Change-Id: Id3d03e585746aa5509c6fab7d88183a92d561e3f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
* changes:
arm_fpga: Read UART address from DT
arm_fpga: Read GICD and GICR base addresses from DT
arm_fpga: Read generic timer counter frequency from DT
arm_fpga: Use Generic UART
This patch validates that PSTATE_STANDBY is set as the C6 power state type.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I26a4a61bcb4ee0d1846ab61c007eeba3c180e5aa
Tegra194 platforms removed support to power down CPUs during CPU suspend. This
patch removes the support for CPU suspend power down as a result.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifde72c90c194582a79fb80904154b9886413f16e
The arm_fpga port requires a DTB, to launch a BL33 payload.
To make this port more flexible, we can also use the information in the
DT to configure the console driver.
For a start, find the DT node pointed to by the stdout-path property, and
read the base address from there.
This assumes for now that the stdout-path points to a PL011 UART.
This allows to remove platform specific addresses from the image. We
keep the original base address for the crash console.
Change-Id: I46a990de2315f81cae4d7913ae99a07b0bec5cb1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Now that we have an implementation for getting the node offset of the
stdout-path property in the generic fdt_wrappers code, use that to
replace the current ST platform specific implementation.
Change-Id: I5dd05684e7ca3cb563b5f71c885e1066393e057e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Since we use a DTB with all platform information to pass this on to a
kernel loaded as BL33, we can as well make use of it for our own
purposes.
Every DT would contain a node for the GIC(v3) interrupt controller, so
we can read the base address for the distributor and redistributors from
there.
This avoids hard coding this information in the code and allows for a more
flexible binary.
Change-Id: Ic530e223a21a45bc30a07a21048116d5af69e972
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The stdout-path property in the /chosen node of a DTB points to a device
node, which is used for boot console output.
On most (if not all) ARM based platforms this is the debug UART.
The ST platform code contains a function to parse this property and
chase down eventual aliases to learn the node offset of this UART node.
Introduce a slightly more generalised version of this ST platform function
in the generic fdt_wrappers code. This will be useful for other platforms
as well.
Change-Id: Ie6da47ace7833861b5e35fe8cba49835db3659a5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The ARM Generic Timer DT binding describes an (optional) property to
declare the counter frequency. Its usage is normally discouraged, as the
value should be read from the CNTFRQ_EL0 system register.
However in our case we can use it to program this register in the first
place, which avoids us to hard code a counter frequency into the code.
We keep some default value in, if the DT lacks that property for
whatever reason.
Change-Id: I5b71176db413f904f21eb16f3302fbb799cb0305
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The STM32 platform port parse DT nodes to find base address to
peripherals. It does this by using its own implementation, even though
this functionality is generic and actually widely useful outside of the
STM32 code.
Re-implement fdt_get_reg_props_by_name() on top of the newly introduced
fdt_get_reg_props_by_index() function, and move it to fdt_wrapper.c.
This is removes the assumption that #address-cells and #size-cells are
always one.
Change-Id: I6d584930262c732b6e0356d98aea50b2654f789d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The SCP firmware on the ARM FPGA initialises the UART already. This allows
us to treat the PL011 as an SBSA Generic UART, which does not require
any further setup.
This in particular removes the need for any baudrate and base clock related
settings to be hard coded into the BL31 image.
Change-Id: I16fc943526267356b97166a7068459e06ff77f0f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
At the moment the fconf_populate_gicv3_config() implementation is
somewhat incomplete: First it actually fails to store the retrieved
information (the local addr[] array is going nowhere), but also it makes
quite some assumptions about the device tree passed to it: it needs to
use two address-cells and two size-cells, and also requires all five
register regions to be specified, where actually only the first two
are mandatory according to the binding (and needed by our code).
Fix this by introducing a proper generic function to retrieve "reg"
property information from a DT node:
We retrieve the #address-cells and #size-cells properties from the
parent node, then use those to extract the right values from the "reg"
property. The function takes an index to select one region of a reg
property.
This is loosely based on the STM32 implementation using "reg-names",
which we will subsume in a follow-up patch.
Change-Id: Ia59bfdf80aea4e36876c7b6ed4d153e303f482e8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Dynamic configuration properties are fconf properties. Modify the
compatible string from "arm,.." to "fconf,.." to reflect this.
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Change-Id: I85eb75cf877c5f4d3feea3936d4c348ca843bc6c
The STM32 platform code uses its own set of FDT helper functions,
although some of them are fairly generic.
Remove the implementation of fdt_read_uint32_default() and implement it
on top of the newly introduced fdt_read_uint32() function, then convert
all users over.
This also fixes two callers, which were slightly abusing the "default"
semantic.
Change-Id: I570533362b4846e58dd797a92347de3e0e5abb75
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Our fdtw_read_cells() implementation goes to great lengths to
sanity-check every parameter and result, but leaves a big hole open:
The size of the storage the value pointer points at needs to match the
number of cells given. This can't be easily checked at compile time,
since we lose the size information by using a void pointer.
Regardless the current usage of this function is somewhat wrong anyways,
since we use it on single-element, fixed-length properties only, for
which the DT binding specifies the size.
Typically we use those functions dealing with a number of cells in DT
context to deal with *dynamically* sized properties, which depend on
other properties (#size-cells, #clock-cells, ...), to specify the number
of cells needed.
Another problem with the current implementation is the use of
ambiguously sized types (uintptr_t, size_t) together with a certain
expectation about their size. In general there is no relation between
the length of a DT property and the bitness of the code that parses the
DTB: AArch64 code could encounter 32-bit addresses (where the physical
address space is limited to 4GB [1]), while AArch32 code could read
64-bit sized properties (/memory nodes on LPAE systems, [2]).
To make this more clear, fix the potential issues and also align more
with other DT users (Linux and U-Boot), introduce functions to explicitly
read uint32 and uint64 properties. As the other DT consumers, we do this
based on the generic "read array" function.
Convert all users to use either of those two new functions, and make
sure we never use a pointer to anything other than uint32_t or uint64_t
variables directly.
This reveals (and fixes) a bug in plat_spmd_manifest.c, where we write
4 bytes into a uint16_t variable (passed via a void pointer).
Also we change the implementation of the function to better align with
other libfdt users, by using the right types (fdt32_t) and common
variable names (*prop, prop_names).
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi#n874
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/ecx-2000.dts
Change-Id: I718de960515117ac7a3331a1b177d2ec224a3890
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The device tree parsing code for the STM32 platform is using its own FDT
helper functions, some of them being rather generic.
In particular the existing fdt_read_uint32_array() implementation is now
almost identical to the new generic code in fdt_wrappers.c, so we can
remove the ST specific version and adjust the existing callers.
Compared to the original ST implementation the new version takes a
pointer to the DTB as the first argument, and also swaps the order of
the number of cells and the pointer.
Change-Id: Id06b0f1ba4db1ad1f733be40e82c34f46638551a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Currently our fdtw_read_array() implementation requires the length of
the property to exactly match the requested size, which makes it less
flexible for parsing generic device trees.
Also the name is slightly misleading, since we treat the cells of the
array as 32 bit unsigned integers, performing the endianess conversion.
To fix those issues and align the code more with other DT users (Linux
kernel or U-Boot), rename the function to "fdt_read_uint32_array", and
relax the length check to only check if the property covers at least the
number of cells we request.
This also changes the variable names to be more in-line with other DT
users, and switches to the proper data types.
This makes this function more useful in later patches.
Change-Id: Id86f4f588ffcb5106d4476763ecdfe35a735fa6c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Make sure the string generated in unsigned_num_print() is zero-terminated.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ic0ac1ebca255002522159a9152ab41991f043d05
Move the data section to the common header.
I slightly tweaked some scripts as follows:
[1] bl1.ld.S has ALIGN(16). I added DATA_ALIGN macro, which is 1
by default, but overridden by bl1.ld.S. Currently, ALIGN(16)
of the .data section is redundant because commit 4128659076
("Fix boot failures on some builds linked with ld.lld.") padded
out the previous section to work around the issue of LLD version
<= 10.0. This will be fixed in the future release of LLVM, so
I am keeping the proper way to align LMA.
[2] bl1.ld.S and bl2_el3.ld.S define __DATA_RAM_{START,END}__ instead
of __DATA_{START,END}__. I put them out of the .data section.
[3] SORT_BY_ALIGNMENT() is missing tsp.ld.S, sp_min.ld.S, and
mediatek/mt6795/bl31.ld.S. This commit adds SORT_BY_ALIGNMENT()
for all images, so the symbol order in those three will change,
but I do not think it is a big deal.
Change-Id: I215bb23c319f045cd88e6f4e8ee2518c67f03692
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The stacks section is the same for all BL linker scripts.
Move it to the common header file.
Change-Id: Ibd253488667ab4f69702d56ff9e9929376704f6c
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
RD-Daniel Config-XLR platform has four identical chips connected via a
high speed coherent CCIX link. Each chip has four Neoverse cores
connected via coherent CMN interconnect.
Change-Id: I37d1b91f2b6ba08f61c64d0288bc16a429836c08
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
This commit fixes an assertion that was triggering in certain contexts:
ERROR: mmap_add_region_check() failed. error -22
ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:790
Change-Id: Ia55b3fb4f496c8cd791ea6093d122edae0a7e92a
Signed-off-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
By writing 0 to CLUSTERPWRDN DSU register bit 0, we send an
advisory to the power controller that cluster power is not required
when all cores are powered down.
The AArch32 CLUSTERPWRDN register is architecturally mapped to the
AArch64 CLUSTERPWRDN_EL1 register
Change-Id: Ie6e67c1c7d811fa25c51e2e405ca7f59bd20c81b
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
A single chip platform requires five mmap entries and a corresponding
number of translation tables. For every additional chip in the system,
three additional mmap entries are required to map the shared SRAM and
the IO regions. A corresponding number of additional translation
tables are required as well.
Change-Id: I1332a1305f2af62181387cf36954f6fb0e6f11ed
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
The arm_fpga platform code contains an dubious line to initialise some
timer. On closer inspection this turn out to be bogus, as this was only
needed on some special (older) FPGA board, and is actually not needed on
the current model. Also the base address was wrong anyways.
Remove the code entirely.
Change-Id: I02e71aea645051b5addb42d972d7a79f04b81106
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
RD-Daniel uses GIC-Clayton as its interrupt controller which is an
implementation of GICv4.1 architecture. Hence for RD-Daniel, enable
GICv4 extension support.
Change-Id: I45ae8c82376f8fe8fc0666306822ae2db74e71b8
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
This patch adds support for GICv4 extension for FVP platform.
Change-Id: Ia389b61266af669b1ca9b999a8b76476cab214f4
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Increased the maximum size of BL2 image in order to
accommodate the BL2 image when TF-A build with no compiler
optimization for ARM platform.
Note: As of now, "no compiler optimization" build works
only when TRUSTED_BOOT_BOARD option is set to 0.
This change is verified using below CI configuration:
1. juno-no-optimize-default:juno-linux.uboot
2. fvp-no-optimize-default,fvp-default:fvp-tftf-fip.tftf-aemv8a-debug
Change-Id: I5932621237f8acd1b510682388f3ba78eae90ea4
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Default board configuration was set to bcm958742k which is not present
in current codebase. This causes a default platform build to fail.
Changing to bcm958742t.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Ie24f94ef0ef316ff56fe142df5de45d70ba93c28
with commit a6ea06f5, the way platform includes gicv3 files has been
modified, this patch adapts to new method of including gicv3 files
for arm_fpga platform.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ic5ccae842b39b7db06d4f23c5738b174c42edf63
* changes:
doc: brcm: Add documentation file for brcm stingray platform
drivers: Add SPI Nor flash support
drivers: Add iproc spi driver
drivers: Add emmc driver for Broadcom platforms
Add BL31 support for Broadcom stingray platform
Add BL2 support for Broadcom stingray platform
Add bl31 support common across Broadcom platforms
Add bl2 setup code common across Broadcom platforms
drivers: Add support to retrieve plat_toc_flags
The platform io policies array is now always accessed through a fconf getter.
This gives us an ideal spot to check for out-of-bound accesses.
Remove the assertion in plat_get_image_source(), which is now redundant.
Change-Id: Iefe808d530229073b68cbd164d927b8b6662a217
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* changes:
xlat_tables_v2: fix assembler warning of PLAT_RO_XLAT_TABLES
linker_script: move bss section to bl_common.ld.h
linker_script: replace common read-only data with RODATA_COMMON
linker_script: move more common code to bl_common.ld.h
This is not used in BL31 or Bl32 for this platform.
Pass it to BL2_CPPFLAGS instead of defining it for all BL images.
This will produce slightly smaller BL31 and Bl32.
Change-Id: I66ec5179f8dc5b112e65547335e7dd0a0f4074cd
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
As GCC manual says, -D option defines a macro as 1, if =<value> is omitted.
-D <name>
Predefine <name> as a macro, with definition 1.
The same applied with Clang, too.
In the context of -D option, =1 is always redundant.
Change-Id: I487489a1ea3eb51e734741619c1e65dab1420bc4
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Commit d5e97a1d2c ("Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3
globally for C files") does not have commit 848a7e8ce1 ("Build:
introduce per-BL CPPFLAGS and ASFLAGS") as an ancestor because
they were pulled almost at the same time.
This is a follow-up conversion to be consistent with commit
11a3c5ee73 ("plat: pass -D option to BL*_CPPFLAGS instead of
BL*_CFLAGS").
With this change, the command line option, IMAGE_AT_EL3, will be
passed to .S files as well.
I remove the definition in include/lib/cpus/aarch64/cpu_macros.S
Otherwise, the following error would happen.
include/lib/cpus/aarch64/cpu_macros.S:29:0: error: "IMAGE_AT_EL3" redefined [-Werror]
Change-Id: I943c8f22356483c2ae3c57b515c69243a8fa6889
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Move the bss section to the common header. This adds BAKERY_LOCK_NORMAL
and PMF_TIMESTAMP, which previously existed only in BL31. This is not
a big deal because unused data should not be compiled in the first
place. I believe this should be controlled by BL*_SOURCES in Makefiles,
not by linker scripts.
I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3,
BL31, BL31 for plat=uniphier. I did not see any more unexpected
code addition.
The bss section has bigger alignment. I added BSS_ALIGN for this.
Currently, SORT_BY_ALIGNMENT() is missing in sp_min.ld.S, and with this
change, the BSS symbols in SP_MIN will be sorted by the alignment.
This is not a big deal (or, even better in terms of the image size).
Change-Id: I680ee61f84067a559bac0757f9d03e73119beb33
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The common section data are repeated in many linker scripts (often
twice in each script to support SEPARATE_CODE_AND_RODATA). When you
add a new read-only data section, you end up with touching lots of
places.
After this commit, you will only need to touch bl_common.ld.h when
you add a new section to RODATA_COMMON.
Replace a series of RO section with RODATA_COMMON, which contains
6 sections, some of which did not exist before.
This is not a big deal because unneeded data should not be compiled
in the first place. I believe this should be controlled by BL*_SOURCES
in Makefiles, not by linker scripts.
When I was working on this commit, the BL1 image size increased
due to the fconf_populator. Commit c452ba159c ("fconf: exclude
fconf_dyn_cfg_getter.c from BL1_SOURCES") fixed this issue.
I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3,
BL31, BL31 for plat=uniphier. I did not see any more unexpected
code addition.
Change-Id: I5d14d60dbe3c821765bce3ae538968ef266f1460
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
These are mostly used to collect data from special structure,
and repeated in many linker scripts.
To differentiate the alignment size between aarch32/aarch64, I added
a new macro STRUCT_ALIGN.
While I moved the PMF_SVC_DESCS, I dropped #if ENABLE_PMF conditional.
As you can see in include/lib/pmf/pmf_helpers.h, PMF_REGISTER_SERVICE*
are no-op when ENABLE_PMF=0. So, pmf_svc_descs and pmf_timestamp_array
data are not populated.
Change-Id: I3f4ab7fa18f76339f1789103407ba76bda7e56d0
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This patch enables the Exception Handling Framework to service the WDT
interrupts on all Tegra platforms.
Verified that the watchdog timer interrupt fires after migrating to
the EHF.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I6b2e33da7841aa064e3a8f825c26fadf168cd0d5
We simulate the PSCI CPU_OFF operation by reseting the core via RMR.
For secondaries, that already puts them in the holding pen waiting for a
"warm boot" request as part of PSCI CPU_ON. For the BSP, we have to add
logic to distinguish a regular boot from a CPU_OFF state, where, like the
secondaries, the BSP needs to wait foor a "warm boot" request as part
of CPU_ON.
Testing done:
- ACS suite now passes more tests (since it repeatedly
calls code on secondaries via CPU_ON).
- Linux testing including offlining/onlineing CPU0, e.g.
"echo 0 > /sys/devices/system/cpu/cpu0/online".
Change-Id: Id0ae11a0ee0721b20fa2578b54dadc72dcbd69e0
Link: https://developer.trustedfirmware.org/T686
Signed-off-by: Andrei Warkentin <andrey.warkentin@gmail.com>
[Andre: adapt to unified plat_helpers.S, smaller fixes]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
When writing to arbitrary locations in memory using a constructed
pointer, there is no guarantee that the compiler does not optimise away
the access, since it cannot detect any dependency.
One typical solution is to use the "volatile" keyword, but using MMIO
accessors in usually the better answer, to avoid torn writes.
Replace the usage of an array with such an MMIO accessor function in
rpi3_pwr_domain_on(), to make sure the write is really happening.
Change-Id: Ia18163c95e92f1557471089fd18abc6dc7fee0c7
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The plat_helpers.S file was almost identical between its RPi3 and RPi4
versions. Unify the two files, moving it into the common/ directory.
This adds a plat_rpi_get_model() function, which can be used to trigger
RPi4 specific action, detected at runtime. We use that to do the RPi4
specific L2 cache initialisation.
Change-Id: I2295704fd6dde7c76fe83b6d98c7bf998d4bf074
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
BL2 for this platform uses mmap_add_dynamic_region(), but BL31 and
BL32 (TSP) only use static mapping. So, BL31 and BL32 can make the
tables read-only after enabling MMU.
Enable ALLOW_RO_XLAT_TABLES by default.
Change-Id: Ib59c44697163629119888bb6abd47fa144f09ba3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, enable_mmu_el1() or enable_mmu_el3() is kept outside the
common function because the appropriate one must be chosen.
Use enable_mmu() and move it to the common function.
Change-Id: If2fb651691a7b6be05674f5cf730ae067ba95d4b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
-D is a preprocessor flag that defines a macro. So, adding it to
BL*_CPPFLAGS makes more sense. You can reference it not only from
.c files but also from .S files.
Change-Id: Ib4f2f27a3ed3eae476a6a32da7ab5225ad0649de
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
1. Necessary changes to platform makefile to include fw_config
device tree and package it in fip.bin
2. Removed hw_config node from fw_config dts as there is no
HW_CONFIG device tree source for sgm775
3. Added mbedtls_heap related properties for TBBR functionality
Change-Id: I26b940c65b17ad2fb5537141f8649785bb0fd4ad
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* changes:
stm32mp1: use stm32mp_get_ddr_ns_size() function
stm32mp1: set XN attribute for some areas in BL2
stm32mp1: dynamically map DDR later and non-cacheable during its test
stm32mp1: add a function to get non-secure DDR size
Moved SMCCC defines from plat_arm.h to new <smccc_def.h> header
and include this header in all ARM platforms.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I4cbc69c7b9307461de87b7c7bf200dd9b810e485
This patch moves all GICv3 driver files into new added
'gicv3.mk' makefile for the benefit of the generic driver
which can evolve in the future without affecting platforms.
The patch adds GICv3 driver configuration flags
'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and
'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in
'GICv3 driver options' section of 'build-option.rst'
document.
NOTE: Platforms with GICv3 driver need to be modified to
include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles.
Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Use ARRAY_SIZE macro instead of sizeof operator to obtain the maximum
number of SCMI channels supported on the platform.
Change-Id: Id922bb548af98ac99b4ac0c34e38e589e5a80b2d
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
* changes:
plat/arm/board/arm_fpga: Compile with additional CPU libraries
plat/arm/board/arm_fpga: Enable position-independent execution
plat/arm/board/arm_fpga: Enable port for alternative cluster configurations
plat/arm/board/arm_fpga: Initialize the Generic Interrupt Controller
plat/arm/board/arm_fpga: Initialize the System Counter
plat/arm/board/arm_fpga: Add PSCI implementation for FPGA images
plat/arm/board/arm_fpga: Use preloaded BL33 alternative boot flow
plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image
On DynamIQ CPU FVPs, stats test cases are failing when
hardware-assisted coherency is enabled due to a corrupt
timestamp value. Investigation of the issue indicates that
on these models the timestamp value is stored in cache
instead of memory. This patch flushes the dcache when the
timestamp is stored to make sure it is stored in memory.
Change-Id: I05cd54ba5991a5a96dd07f1e08b5212273201411
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
This change is part of the goal of enabling the port to be compatible
with multiple FPGA images.
BL31 behaves differently depending on whether or not the CPUs in the
system use cache coherency, and as a result any CPU libraries that are
compiled together must serve processors that are consistent in this
regard.
This compiles a different set of CPU libraries depending on whether or
not the HW_ASSISTED_COHERENCY is enabled at build-time to indicate the
CPUs support hardware-level support for cache coherency. This build
flag is used in the makefile in the same way as the Arm FVP port.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I18300b4443176b89767015e3688c0f315a91c27e
This allows the BL31 port to run with position-independent execution
enabled so that it can be ran from any address in the system.
This increases the flexibility of the image, allowing it to be ran from
other locations rather than only its hardcoded absolute address
(currently set to the typical DRAM base of 2GB). This may be useful for
future images that describe system configurations with other memory
layouts (e.g. where SRAM is included).
It does this by setting ENABLE_PIE=1 and changing the absolute
address to 0. The load address of bl31.bin can then be specified by
the -l [load address] argument in the fpga-run command (additionally,
this address is required by any preceding payloads that specify the
start address. For ELF payloads this is usually extracted automatically
by reading the entrypoint address in the header, however bl31.bin is a
different file format so has this additional dependency).
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: Idd74787796ab0cf605fe2701163d9c4b3223a143
This change is part of the goal of enabling the port to be compatible
with multiple FPGA images.
The BL31 port that is uploaded as a payload to the FPGA with an image
should cater for a wide variety of system configurations. This patch
makes the necessary changes to enable it to function with images whose
cluster configurations may be larger (either by utilizing more
clusters, more CPUs per cluster, more threads in each CPU, or a
combination) than the initial image being used for testing.
As part of this, the hard-coded values that configure the size of the
array describing the topology of the power domain tree are increased
to max. 8 clusters, max. 8 cores per cluster & max 4 threads per core.
This ensures the port works with cluster configurations up to these
sizes. When there are too many entries for the number of available PEs,
e.g. if there is a variable number of CPUs between clusters, then there
will be empty entries in the array. This is permitted and the PSCI
library will still function as expected. While this increases its size,
this shouldn't be an issue in the context of the size of BL31, and is
worth the trade-off for the extra compatibility.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I7d4ae1e20b2e99fdbac428d122a2cf9445394363
This initializes the GIC using the Arm GIC drivers in TF-A.
The initial FPGA image uses a GIC600 implementation, and so that its
power controller is enabled, this platform port calls the corresponding
implementation-specific routines.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I88d5a073eead4b653b1ca73273182cd98a95e4c5
This sets the frequency of the system counter so that the Delay Timer
driver programs the correct value to CNTCRL. This value depends on
the FPGA image being used, and is 10MHz for the initial test image.
Once configured, the BL31 platform setup sequence then enables the
system counter.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: Ieb036a36fd990f350b5953357424a255b8ac5d5a
This adds a basic PSCI implementation allow secondary CPUs to be
released from an initial state and continue through to the warm boot
entrypoint.
Each secondary CPU is kept in a holding pen, whereby it polls the value
representing its hold state, by reading this from an array that acts as
a table for all the PEs. The hold states are initially set to 0 for all
cores to indicate that the executing core should continue polling.
To prevent the secondary CPUs from interfering with the platform's
initialization, they are only updated by the primary CPU once the cold
boot sequence has completed and fpga_pwr_domain_on(mpidr) is called.
The polling target CPU will then read 1 (which indicates that it should
branch to the warm reset entrypoint) and then jump to that address
rather than continue polling.
In addition to the initial polling behaviour of the secondary CPUs
before their warm boot reset sequence, they are also placed in a
low-power wfe() state at the end of each poll; accordingly, the PSCI
fpga_pwr_domain_on(mpidr) function also signals an event to all cores
(after updating the target CPU's hold entry) to wake them from this
state, allowing any secondary CPUs that are still polling to check
their hold state again.
This method is in accordance with both the PSCI and Linux kernel
recommendations, as the lessened overhead reduces the energy
consumption associated with the busy-loop.
The table of hold entries is implemented by a global array as shared SRAM
(which is used by other platforms in similar implementations) is not
available on the FPGA images.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I65cfd1892f8be1dfcb285f0e1e94e7a9870cdf5a
This makes use of the PRELOADED_BL33_BASE flag to indicate to BL31 that
the BL33 payload (kernel) has already been loaded and resides in memory;
BL31 will then jump to the non-secure address.
For this port the BL33 payload is the Linux kernel, and in accordance
with the pre-kernel setup requirements (as specified in the `Booting
AArch64 Linux' documentation:
https://www.kernel.org/doc/Documentation/arm64/booting.txt),
this change also sets up the primary CPU's registers x0-x3 so they are
the expected values, which includes the address of the DTB at x0.
An external linker script is currently required to combine BL31, the
BL33 payload, and any other software images to create an ELF file that
can be uploaded to the FPGA board along with the bit file. It therefore
has dependencies on the value of PRELOADED_BL33_BASE (kernel base) and
the DTB base (plus any other relevant base addresses used to
distinguish the different ELF sections), both of which are set in this
patch.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: If7ae8ee82d1e09fb05f553f6077ae13680dbf66b
This adds the minimal functions and definitions to create a basic
BL31 port for an initial FPGA image, in order for the port to be
uploaded to one the FPGA boards operated by an internal group within
Arm, such that BL31 runs as a payload for an image.
Future changes will enable the port for a wide range of system
configurations running on the FPGA boards to ensure compatibility with
multiple FPGA images.
It is expected that this will replace the FPGA fork of the Linux kernel
bootwrapper by performing similar secure-world initialization and setup
through the use of drivers and other well-established methods, before
passing control to the kernel, which will act as the BL33 payload and
run in EL2NS.
This change introduces a basic, loadable port with the console
initialized by setting the baud rate and base address of the UART as
configured by the Zeus image.
It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
Instead of using dt_get_ddr_size() and withdrawing the secure and shared
memory areas, use stm32mp_get_ddr_ns_size() function.
Change-Id: I5608fd7873589ea0e1262ba7d2ee3e52b53d9a7d
Signed-off-by: Yann Gautier <yann.gautier@st.com>
DTB and BL32 area should not be set as executable in MMU during BL2
execution, hence set those areas as MT_RO_DATA.
Change-Id: I87c47a1e7fda761e541ec98a5b294588384d31db
Signed-off-by: Yann Gautier <yann.gautier@st.com>
A speculative accesses to DDR could be done whereas it was not reachable
and could lead to bus stall.
To correct this the dynamic mapping in MMU is used.
A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute,
once DDR access is setup. It is then unmapped and a new mapping DDR is done
with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE)
load.
The disabling of cache during DDR tests is also removed, as now useless.
A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done
instead.
PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32.
BL33 max size is also updated to take into account the secure and shared
memory areas. Those are used in OP-TEE case.
Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This function gets the DDR size from DT, and withdraws (if defined) the
sizes of secure DDR and shared memory areas.
This function also checks DT values fits the default DDR range.
This non-secure memory is available for BL33 and non-secure OS.
Change-Id: I162ae5e990a0f9b6b7d07e539de029f1d61a391b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This patch increases MAX_MMAP_REGIONS to 30 to accommodate the
additional dynamic memory mapped region, during Trusty boot.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I461186a3aff5040f14715b87502fc5f1db3bea6e
This patch provides support for measured boot by adding calculation
of BL2 image hash in BL1 and writing these data in TB_FW_CONFIG DTB.
Change-Id: Ic074a7ed19b14956719c271c805b35d147b7cec1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This patch increases the maximum timeout value for SE operation
completion to 1 second. This takes care of some corner cases where
an operation might take more time than the previous timeout value
of 100ms.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I0012448ba372a8bb0e156df7dfe49d7de6d21a68
When SPD=spmd and SPMD_SPM_AT_SEL2=0, that is SPMC sits at S-EL1
then there is no need for TF-A to load secure partitions individually.
In this configuration, SPMC handles secure partition loading at
S-EL1/EL0 levels.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I06a0d88a4811274a8c347ce57b56bb5f64e345df
This warning was issued by cppcheck in our downstream code:
[plat/st/common/stm32mp_dt.c:629] -> [plat/st/common/stm32mp_dt.c:634]:
(warning) Identical condition 'node<0', second condition is always false
The second test has to check variable pwr_regulators_node.
Change-Id: I4a20c4a3ac0ef0639c2df36309d90a61c02b511f
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Correct the following sparse warnings:
plat/st/common/stm32mp_dt.c:103:5: warning:
symbol 'fdt_get_node_parent_address_cells' was not declared.
Should it be static?
plat/st/common/stm32mp_dt.c:123:5: warning:
symbol 'fdt_get_node_parent_size_cells' was not declared.
Should it be static?
As those 2 functions are only used by assert(), put them under
ENABLE_ASSERTIONS flag.
Change-Id: Iad721f12128df83a3de3f53e7920a9c1dce64c56
Signed-off-by: Yann Gautier <yann.gautier@st.com>
1. This removes hardcoded iomux/clk/addr configuration for debug uart,
provides possibility (as a workaround, till that information isn't
provided via DT) to set this configuration during compile time via
IMX_DEBUG_UART build flag.
Also for Colibri i.MX8QXP different pinmux configuration is applied
for UART3, FLEXCAN2_RX/TX pads are muxed to ADMA_UART3_RX/TX.
2. Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A35
doesn't make sense (since UART pinmux/clock configuration is applied
for UART only when DEBUG_CONSOLE_A35 is enabled. Check similar commit
for i.MX8QM 98a69dfd4a("plat: imx: imx8qm: apply clk/pinmux
configuration for DEBUG_CONSOLE")).
Usage:
$ make PLAT=imx8qx IMX_DEBUG_UART=3 DEBUG_CONSOLE=1 bl31
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: I5d04939b2e8ee1a5f4b2f3c6241977d3c6e91760
* changes:
Tegra194: move cluster and CPU counter to header file.
Tegra: gicv2: initialize target masks
spd: tlkd: support new TLK SMCs for RPMB service
Tegra210: trigger CPU0 hotplug power on using FC
Tegra: memctrl: cleanup streamid override registers
Tegra: memctrl_v2: remove support to secure TZSRAM
Tegra: include platform headers from individual makefiles
Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro
Tegra194: SiP function ID to read SMMU_PER registers
Tegra: memctrl: map video memory as uncached
Tegra: remove support for USE_COHERENT_MEM
Tegra: remove circular dependency with common_def.h
Tegra: include missing stdbool.h
Tegra: remove support for SEPARATE_CODE_AND_RODATA=0
The base address for both the GPIO and the clock unit of the H6 memory map
have been typo-ed. Fix them to match the Linux DT and the manual.
The H6 code use neither of them, so this doesn't change or fix anything
in the real world, but should be corrected anyway.
The issue was found and reported by Github user "armlabs".
Change-Id: Ic6fdfb732ce1cfc54cbb927718035624a06a9e08
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Commit e9e19fb2fe accidentally removed the
GIC init routine required to initialze the distributor on system resume.
This patch fixes this anomaly and initializes the distributor on system
resume.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3fdc694404faa509952f2d90b1f16541165e583e
MISRA rules request that the cluster and CPU counter be unsigned
values and have a suffix 'U'. If the define located in the makefile,
this cannot be done.
This patch moves the PLATFORM_CLUSTER_COUNT and PLATFORM_MAX_CPUS_PER_CLUSTER
macros to tegra_def.h as a result.
Change-Id: I9ef0beb29485729de204b4ffbb5241b039690e5a
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
This patch initializes the target masks in the GICv2 driver
data, for all PEs. This will allow platforms to set the PE
target for SPIs.
Change-Id: I7bf2ad79c04c2555ab310acba17823fb157327a3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Hotplug poweron is not working for boot CPU as it's being
triggerred using PMC and not with Flow Controller. This is
happening because "cpu_powergate_mask" is only getting set
for non-boot CPU's as the boot CPU's first bootup follows
different code path. The patch is marking a CPU as ON within
"cpu_powergate_mask" when turning its power domain on
during power on. This will ensure only first bootup on all
CPU's is using PMC and subsequent hotplug poweron will be
using Flow Controller.
Change-Id: Ie9e86e6f9a777d41508a93d2ce286f31307932c2
Signed-off-by: sumitg <sumitg@nvidia.com>
Streamid override registers are passed to memctrl to program bypass
streamid for all the registers. There is no reason to bypass SMMU
for any of the client so need to remove register list and do not
set streamid_override_cfg.
Some Tegra186 platforms don't boot due to SDMMC failure so keep SDMMC
bypass as of now. Will revisit once these issues are fixed.
Change-Id: I3f67e2a0e1b53160e2218f3acace7da45532f934
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
This patch removes support to secure the on-chip TZSRAM memory for
Tegra186 and Tegra194 platforms as the previous bootloader does that
for them.
Change-Id: I50c7b7f9694285fe31135ada09baed1cfedaaf07
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch modifies PLAT_INCLUDES to include individual Tegra SoC
headers from the platform's makefile.
Change-Id: If5248667f4e58ac18727d37a18fbba8e53f2d7b5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch renames 'ENABLE_WDT_LEGACY_FIQ_HANDLING' macro to
'ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING', to indicate that this
is a Tegra feature.
Change-Id: I5c4431e662223ee80efbfd5ec2513f8b1cadfc50
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch introduces SiP function ID, 0xC200FF00, to read SMMU_PER
error records from all supported SMMU blocks.
The register values are passed over to the client via CPU registers
X1 - X3, where
X1 = SMMU_PER[instance #1] | SMMU_PER[instance #0]
X2 = SMMU_PER[instance #3] | SMMU_PER[instance #2]
X3 = SMMU_PER[instance #5] | SMMU_PER[instance #4]
Change-Id: Id56263f558838ad05f6021f8432e618e99e190fc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Memmap video memory as uncached normal memory by adding flag
'MT_NON_CACHEABLE' in mmap_add_dynamic_region().
This improves the time taken for clearing the non-overlapping video
memory:
test conditions: 32MB memory size, EMC running at 1866MHz, t186
1) without MT_NON_CACHEABLE: 30ms ~ 40ms
<3>[ 133.852885] vpr-heap: update vpr base to 0x00000000c6000000, size=e000000
<3>[ 133.860471] _tegra_set_vpr_params[120]: begin
<3>[ 133.896481] _tegra_set_vpr_params[123]: end
<3>[ 133.908944] vpr-heap: update vpr base to 0x00000000c6000000, size=c000000
<3>[ 133.916397] _tegra_set_vpr_params[120]: begin
<3>[ 133.956369] _tegra_set_vpr_params[123]: end
<3>[ 133.970394] vpr-heap: update vpr base to 0x00000000c6000000, size=a000000
<3>[ 133.977934] _tegra_set_vpr_params[120]: begin
<3>[ 134.013874] _tegra_set_vpr_params[123]: end
<3>[ 134.025666] vpr-heap: update vpr base to 0x00000000c6000000, size=8000000
<3>[ 134.033512] _tegra_set_vpr_params[120]: begin
<3>[ 134.065996] _tegra_set_vpr_params[123]: end
<3>[ 134.075465] vpr-heap: update vpr base to 0x00000000c6000000, size=6000000
<3>[ 134.082923] _tegra_set_vpr_params[120]: begin
<3>[ 134.113119] _tegra_set_vpr_params[123]: end
<3>[ 134.123448] vpr-heap: update vpr base to 0x00000000c6000000, size=4000000
<3>[ 134.130790] _tegra_set_vpr_params[120]: begin
<3>[ 134.162523] _tegra_set_vpr_params[123]: end
<3>[ 134.172413] vpr-heap: update vpr base to 0x00000000c6000000, size=2000000
<3>[ 134.179772] _tegra_set_vpr_params[120]: begin
<3>[ 134.209142] _tegra_set_vpr_params[123]: end
2) with MT_NON_CACHEABLE: 10ms ~ 18ms
<3>[ 102.108702] vpr-heap: update vpr base to 0x00000000c6000000, size=e000000
<3>[ 102.116296] _tegra_set_vpr_params[120]: begin
<3>[ 102.134272] _tegra_set_vpr_params[123]: end
<3>[ 102.145839] vpr-heap: update vpr base to 0x00000000c6000000, size=c000000
<3>[ 102.153226] _tegra_set_vpr_params[120]: begin
<3>[ 102.164201] _tegra_set_vpr_params[123]: end
<3>[ 102.172275] vpr-heap: update vpr base to 0x00000000c6000000, size=a000000
<3>[ 102.179638] _tegra_set_vpr_params[120]: begin
<3>[ 102.190342] _tegra_set_vpr_params[123]: end
<3>[ 102.197524] vpr-heap: update vpr base to 0x00000000c6000000, size=8000000
<3>[ 102.205085] _tegra_set_vpr_params[120]: begin
<3>[ 102.216112] _tegra_set_vpr_params[123]: end
<3>[ 102.224080] vpr-heap: update vpr base to 0x00000000c6000000, size=6000000
<3>[ 102.231387] _tegra_set_vpr_params[120]: begin
<3>[ 102.241775] _tegra_set_vpr_params[123]: end
<3>[ 102.248825] vpr-heap: update vpr base to 0x00000000c6000000, size=4000000
<3>[ 102.256069] _tegra_set_vpr_params[120]: begin
<3>[ 102.266368] _tegra_set_vpr_params[123]: end
<3>[ 102.273400] vpr-heap: update vpr base to 0x00000000c6000000, size=2000000
<3>[ 102.280672] _tegra_set_vpr_params[120]: begin
<3>[ 102.290929] _tegra_set_vpr_params[123]: end
Change-Id: I5f604064ce7b8b73ea9ad5860156ae5e2c6cc42a
Signed-off-by: Ken Chang <kenc@nvidia.com>
This patch removes the support for 'USE_COHERENT_MEM' as
Tegra platforms no longer support the feature.
Change-Id: If1c80fc4e5974412572b3bc1fdf9e70b1ee5d4ec
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
This patch stops including common_def.h from platform_def.h to
fix a circular depoendency between them.
This means platform_def.h now has to define the linker macros:
* PLATFORM_LINKER_FORMAT
* PLATFORM_LINKER_ARCH
Change-Id: Icd540b1bd32fb37e0e455e9146c8b7f4b314e012
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch includes the missing stdbool.h header from flowctrl.h
and bpmp_ivc.c files.
Change-Id: If60d19142b1cb8ae663fbdbdf1ffe45cbbdbc1b2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Tegra platforms will not be supporting SEPARATE_CODE_AND_RODATA=0.
This patch uses the common macros provided by bl_common.h as a result
and adds a check to assert if SEPARATE_CODE_AND_RODATA set is not set
to '1'.
Change-Id: I376ea60c00ad69cb855d89418bdb80623f14800e
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
To demonstrate communication between SP's two instances of Cactus at
S-EL1 has been used.
This patch replaces Ivy SP with cactus-secondary SP which aligns with
changes in tf-a-tests repository.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Iee84f1f7f023b7c4f23fbc13682a42614a7f3707
When using the SPM Dispatcher, the SPMC sits as a BL32 component
(BL32_IMAGE_ID). The SPMC manifest is passed as the TOS fw config
component (TOS_FW_CONFIG_ID). It defines platform specific attributes
(memory range and physical CPU layout) as well as the attributes for
each secure partition (mostly load address). This manifest is passed
to the SPMC on boot up. An SP package contains the SP dtb in the SPCI
defined partition manifest format. As the SPMC manifest was enriched
it needs an increase of tos_fw-config max-size in fvp_fw_config dts.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ia1dce00c6c4cbaa118fa56617980d32e2956a94e
The 'plat_core_pos_by_mpidr' handler gets called very early during boot
and the compiler generated code overwrites the caller's registers.
This patch converts the 'plat_core_pos_by_mpidr' handler into an assembly
function and uses registers x0-x3, to fix this anomaly.
Change-Id: I8d974e007a0bad039defaf77b11a180d899ead3c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Sandrine Bailleux
Madhukar Pappireddy
Tien Hock Loh
Hugh Cole-Baker
Manish Pandey
Alex Leibovich
Grzegorz Jaszczyk
Heiko Stuebner
Lauren Wehrmeister
Masahisa Kojima
Etienne Carriere
Marcin Wojtas
Jimmy Brisson
Jan Kiszka
Mark Dykes
Alexei Fedorov
Usama Arif
Manish V Badarkhe
J-Alves
Jacky Bai
Varun Wadekar
johpow01
Balint Dobszay
Olivier Deprez
Andre Przywara
Louis Mayencourt
Marek Vasut
Masahiro Yamada
Aditya Angadi
Chris Kay
Sheetal Tigadoli
Vijayenthiran Subramaniam
Max Shvetsov
Javier Almansa Sobrino
Andrei Warkentin
Zelalem
Oliver Swede
Yann Gautier
Igor Opaniuk
Anthony Zhou
sumitg
Pritesh Raithatha
Ken Chang
Kalyani Chidambaram