In a later patch, the stm32mp1_def.h will be reworked. The inclusion
of common/debug.h may not be done there through another included file.
Add this header inclusion in the files that need it.
Change-Id: I83687f7910032ca38c0856796580a650e1e41a68
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Replace wrong %d with the correct types.
This issue was found with the compilation flag:
-Wformat-signedness
Change-Id: Iec3817a245f964ce444b59561b777ce06c51a60a
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Instead of transmitting an 'enum stm32mp_osc_id', just send
directly the clock name with a 'const char *'
Change-Id: I866b05cbb1685a9b9f80e63dcd5ba7b1d35fc932
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
In case of programmer mode, the bootrom manages to auto-detect
HSE clock configuration. In order to detect a bad device tree
setting in BL2, it will crash during programming if the configuration
is not aligned with the auto-detection.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I230697695745d6282d14b1ebfa6e4c4caa0cd8e2
Support "disabled" status for oscillator in device tree.
At boot time, the clock tree initialization performs the following
tasks:
- enabling of the oscillators present in the device tree and not
disabled,
- disabling of the HSI oscillator if the node is absent or disabled
(always activated by bootROM).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I176276022334f3d97ba0250b54062f0ae970e239
Add a function to get PLL settings from DT:
"cfg" property is mandatory, an error is generated if not found.
"frac" is optional, default value is returned if not found.
"csg" is optional too, a boolean value indicates if it has been
found, and its value is updated.
Store each PLL node validity information, this avoids parsing DT
several times.
Change-Id: I039466fbe1e67d160f7112814e7bb63b661804d0
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Measured-Boot and Trusted-Boot are orthogonal to each other and hence
removed dependency of Trusted-Boot on Measured-Boot by making below
changes -
1. BL1 and BL2 main functions are used for initializing Crypto module
instead of the authentication module
2. Updated Crypto module registration macro for MEASURED_BOOT with only
necessary callbacks for calculating image hashes
3. The 'load_auth_image' function is now used for the image measurement
during Trusted or Non-Trusted Boot flow
Change-Id: I3570e80bae8ce8f5b58d84bd955aa43e925d9fff
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* changes:
refactor(st-ddr): move basic tests in a dedicated file
refactor(st-ddr): reorganize generic and specific elements
feat(stm32mp1): allow configuration of DDR AXI ports number
refactor(st-ddr): update parameter array initialization
feat(st-ddr): add read valid training support
refactor(stm32mp1): remove the support of calibration result
fix(st-ddr): correct DDR warnings
* changes:
feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.3
feat(plat/rcar3): modify type for Internal function argument
feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53
fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53
These basic tests are generic and should be used independently of the
driver, depending on the plaftorm characteristics.
Change-Id: I38161b659ef2a23fd30a56e1c9b1bd98461a2fe4
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
stm32mp_ddrctl structure contains DDRCTRL registers definitions.
stm32mp_ddr_info contains general DDR information extracted from DT.
stm32mp_ddr_size moves to the generic side.
stm32mp1_ddr_priv contains platform private data.
stm32mp_ddr_dt_get_info() and stm32mp_ddr_dt_get_param() allow to
retrieve data from DT. They are located in new generic c/h files in
which stm32mp_ddr_param structure is declared. Platform makefile
is updated.
Adapt driver with this new classification.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I4187376c9fff1a30e7a94407d188391547107997
A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default.
It will allow choosing single or dual AXI ports for DDR.
Change-Id: I48826a66a6f4d18df87e081c0960af89ddda1b9d
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Force alignment of the size of parameters array with the expected
value by the binding.
The registers dynamic structs are removed as not used in TF-A.
Change-Id: I7a41f355a435f54fbf23f468cca87c7f8f7e69e8
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Add the read data eye training = training for optimal read valid placement
(RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I7ac1c77c21ebc30315b532741f2f255c2312d5b2
The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when built-in calibration is executed.
The calibration parameters were provided in the device tree by the
optional node "st,phy-cal", activated in ddr helper file by the
compilation flag DDR_PHY_CAL_SKIP and filled with values generated
by CubeMX.
This patch
- updates the binding file to remove "st,phy-cal" support
- updates the device trees and remove the associated defines
- simplifies the STM32MP1 DDR driver and remove the support of
the optional "st,phy-cal"
After this patch the built-in calibration is always executed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I3fc445520c259f7f05730aefc25e64b328bf7159
Replace %d with %u in logs, to avoid warning when
-Wformat-signedness is enabled.
And correct the order of includes.
Change-Id: I7c711a37fc1deceb8853831a8a09ae50422859c9
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
The issue was reported by Coverity [1]. The return of the functions
regulator_disable() and regulator_enable() was not checked.
If they fail, this means there is an issue either with PMIC or I2C.
The board should the stop booting with a panic().
[1] https://scan4.scan.coverity.com/reports.htm#v47771/p11439/mergedDefectId=374565
Change-Id: If5dfd5643c210e03ae4b1f4cab0168c0db89f60e
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The utrd struct is allocated on the stack by ufs_check_resp's caller.
Invalidating the utrd struct is unnecessary since it's only read from,
and can cause other values stored on the stack (e.g. link register) to
be inadvertently invalidated.
Change-Id: Icd455b52beb2677fafc083d68d0bfa0645b7194b
Signed-off-by: Wing Li <wingers@google.com>
For somewhat historical reasons we are doing some initial PMIC regulator
setup in BL31, as U-Boot does not (yet) have a PMIC driver. This worked
fine so far, but there is at least one board (OrangePi 3) that gets upset,
because the Ethernet PHY needs some *coordinated* bringup of *two*
regulators.
To avoid custom hacks, let's introduce a build option to keep doing the
regulator setup in TF-A. Defining SUNXI_SETUP_REGULATORS to 0 will break
support for some devices on some boards in U-Boot (Ethernet and HDMI),
but will allow to bring up the OrangePi 3 in Linux correctly. We keep
the default at 1 to not change the behaviour for all other boards.
After U-Boot gained proper PMIC support at some point in the future, we
will probably change the default to 0, to get rid of the less optimal
PMIC code in TF-A.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie8e2583d0396f6eeaae8ffe6b6190f27db63e2a7
To correctly initialize the MMC devices, a power cycle is required.
For this we need to:
- disable vmmc-supply regulator
- make the power cycle required for SDMMC2 peripheral
- enable regulators
Change-Id: I2be6d9082d1cc4c864a82cf2c31ff8522e2d31a2
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Fixed regulator is mainly used when no pmic is available
Change-Id: Ib6a998684bcb055ba95a093bee563372d9051474
Signed-off-by: Pascal Paillet <p.paillet@st.com>
print_pmic_info_and_debug() prints the PMIC version ID and displays
regulator information if debug is enabled.
It is under DEBUG flag and called after initialize_pmic() in BL2.
Change-Id: Ib81a625740b7ec6abb49cfca05e44c69efaa4718
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Add a regulator framework to:
- provide an interface to consumers and drivers,
- connect consumers with drivers,
- handle most of devicetree-parsing,
- handle always-on and boot-on regulators,
- handle min/max voltages,
Change-Id: I23c939fdef2c71a416c44c9de332f70db0d2aa53
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Add support for ICC, sink mode, bypass mode,
active discharge and list voltages.
Handle LDO3 sink source mode in a different way to avoid
setting voltage while in sink source mode.
Change-Id: Ib1b909fd8a153f542917f650e43e24317a570534
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Add regulators boost, pwr_sw1 and pwr_sw2 regulators related to
USB OTG supply BOOST, SW_OTG and SWIN/SWOUT. These regulators are
needed since manipulated during the suspend/resume power sequence
as per FDT description for stm32mp15x-xxx boards from
STMicroelectronics.
Change-Id: I6217de707e49882bd5a9100db43e0d354908800d
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Store status of dt_pmic_status() as local static variable,
this avoids parsing DT several times.
In the same way, store nodes in dt_pmic_i2c_config() and
in dt_get_pmic_node() as local static variables.
Change-Id: I4585e9dfdde2847a369bffcc6f2b39ecc2b74de1
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
This is mainly a clock interface with clk_ops callbacks.
Those callbacks are: enable, disable, get_rate, set_parent,
and is_enabled.
This framework is compiled for STM32MP1.
Change-Id: I5119a2aeaf103ceaae7a60d9e423caf0c148d794
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Add set_gpio_reset_cfg() to set a pin in its reset configuration:
analog, no-pull, speed low, and its secure configuration, thanks to
stm32_gpio_is_secure_at_reset().
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7b73c3636859f97fcc57f81cf68b42efc727922e
Modify the type of the variable that stores the value for MPIDR
in the internal function from uint64_t to u_register_t.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ib5bda93d5432e0412132bddf41ead8ee3fcf9e46
Add new function so that the value of bit at WUPMSKCA57/53,
which points to CPU other than the BOOT CPU, is 1 at initialization.
Modify sequence so that value of each bit for CPU at WUPMSKCA57/53 is
basically 0 and target bit value is changed to 1 only when CPU_OFF.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id5dafc04e1dbaf265c8b67b903c335bb1af49914
Change internal function to call when updating value for WUPMSKCA57/53.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id20e65e27861dd73a149ff487123859581a9b5c5
The constants BUNDLE_PERIOD_SCALE and PLL_READY_DLY refer to two
multi-bit registers within the Clock Source Low register. These
constants are used as masks for those registers (and values are not
defined since we are writing zeros to them).
Give them the _MASK suffix.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Id469d0ab4c755d2d6a0150a1ade33dd9d0293667
The register at offset 0x1C3 is called Clock Source Low in functional
specification, but we use constant name GLOB_CLK_SRC_LO. Rename it to
RST_CLK_CTRL instead.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: If7ca460cb166f3828678e1e09c4e6caf5bb77770
The register at offset 0x1C1 is called Reset and Clock Control in
functional specification, but we use constant name GLOB_PHY_CTRL0.
Rename it to RST_CLK_CTRL instead.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I5dac8913bd0686d4f5bd74b91cb7d07ba06df72b
Rename the Lane Status 1 register constants from LANE_STATUS1 to
LANE_STAT1, to use an abbreviation similar to that for Lane
Configuration registers (where we use LANE_CFGx instead of LANE_CONFIGx
or LANE_CONFIGURATIONx).
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ie329d5a93615efe261802a2f027475b602a5c840
Rename the Miscellaneous Control register constants from MISC_REGx to
MISC_CTRLx.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I4d43bbda44b090de4ecf2d52cfc468f9683cc3b5
According to the functional specification, the register at offset 0x48
is called Idle Sync Enable, not Unit Control or some such.
Rename the constants.
Only bit 12 of this register is defined, all other bits are reserved.
But for some reason the code needs the default value of the other bits,
so we also rename constant UNIT_CTRL_DEFAULT_VALUE to
IDLE_SYNC_EN_DEFAULT_VALUE.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ia4f80f945a8f31c190cd9a1875d50d892e72825f
Generation Settings registers have the same layout for different
generations and same setting (i.e. Generation 2 Settings 2 register has
the same layout as Generation 3 Settings 2).
So it does not make sense to prefix the constants for Settings 2 with
G3.
Instead change the prefixes to GSx_ for settings register x.
For Settings 2 of Gen 2 and Gen 3 we have some definitions in the first
and some in the second. Move them all to the first defined register (in
this case Gen 2, since the constant for Gen 1 is not defined because it
is not used).
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I15c337eb58aa37fd99fe388fd59373aa325a3a92
Sometimes we call the constants GENx_SET_y, sometimes GENx_SETTINGS_y,
and sometimes GENx_SETTING_y.
Unify this into GENx_SETy.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I3810fb52b2897fe6730ef6e58d434c47cfef14a9
COMPHY register addresses are defined twice
- once for indirect access, where the constants are of the form
COMPHY_<register_name>
- once for direct access, with constants of the form
<register_name>_ADDR
But sometimes the first case also has this _ADDR suffix (and other times
not).
Drop it from those places to unify how we define these registers.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ibf95be8ade231d0e42258f40614a5f0974d280bd
Some register constants are defined with _REG suffix or REG_ prefix, but
others are not. Unify this by dropping these prefixes / suffixes.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I1ba331c0a4686093ee250bcaf3297349956ac9a8
The COMPHY_RESERVED_REG (offset 0x0E) is currently defined between
COMPHY_KVCO_CAL_CTRL (0x02) and COMPHY_DIG_LOOPBACK_EN (0x23).
But this register does not come from PHY lane register space. The
address 0x0E is not relative to PHY lane registers base address.
It only exists in the indirect register space, before PHY lane 2
registers (which start at address 0x200).
Move its definition in the header and add a comment.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ie726384b980ace83d8ea327df09d928db74c2ab7
Move the definitions for the Miscellaneous Control 0 register (offset 0x4F),
to leave the registers sorted according to their offsets.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I9864be5bd00181d21c9334219be4f89c4f032c8b
The register name for the value PHY_GEN_USB3_5G is PHY_GEN_MAX. We
already define the mask constant as PHY_GEN_MAX_MASK. Thus also the
value name should be prefixed with PHY_GEN_MAX_.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ibf72a66d2e65e240ed2cdbc3a301dbd793e2cb34
The register at offset 0x23 is called Digital Loopback Enable, but the
constant is COMPHY_LOOPBACK_REG0, as if there were some LOOPBACK_REG1
register or something, which there is not.
Rename the constant to COMPHY_DIG_LOOPBACK_EN.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ie88bdd864e2c9ab7e8de70ed7f3a13ee8f08ff79
Currently reg_set() and reg_set16() are implemented via
mmio_clrsetbits_32(), meaning that first bits from mask are cleared,
then data bits are set.
But these function are used everywhere according to update semantics,
where only those bits that are in mask are allowed to be changed.
Example from phy-comphy-cp110.c
mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
/* Set PHY datapath width mode for V0 */
mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
/* Set Data bus width USB mode for V0 */
mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
/* Set CORE_CLK output frequency for 250Mhz */
mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
Change the implementation to update semantics by anding data with mask.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ic72a8f64916274e08baef0b3f4c44a4fa07c1a6c
Currently reg_set() and reg_set16() are almost everywhere (both in
phy-comphy-3700.c and phy-comphy-cp110.c) used as if the semantics were
that of register update function (only bits that are set in mask are
updated):
reg_set(addr, data, mask) {
*addr = (*addr & ~mask) | (data & mask);
}
This comes both from names of arguments (data and mask), and from usage.
But both functions are in fact implemented via mmio_clrsetbits_32(), so
they actually first clear bits from mask and then set bits from data:
reg_set(addr, data, mask) {
*addr = (*addr & ~mask) | data;
}
There are only two places where this is leveraged (where some bits are
put into data argument but they are not put into the mask argument).
Fix those two usages to allow to convert the implementation from
clrsetbits semantics to update semantics.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ib29a1dd7edcdee7a39c4752dbc9dfcd600d8cb5c
The comments about selector register values are wrong.
Bit 0 configures only lane 1, bit 4 only lane 0, and bit 8 lanes 0 and
2.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Iffe42374f92654ebe570557e0d462204439cfa31
Fix comment about COMPHY status register. PCIe/GbE0 PHY is on lane 1,
while USB3/GbE1 on lane 0.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I24734a61727d56f6eab2ed1c366d7a1810dbe19d
The current definitions of reference clock speed register values
#define PCIE_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
#define USB3_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
is ambiguous. The name of the constant implies 25 MHz, but the value
implies 30 MHz, which may make the reader think that the setting has
something to do with both values.
In reality, the values have different tables for SerDes and PCIe/USB3
PHY mode. The value for 25 MHz for PCIe/USB3 mode (0x2) is the value
for 30 MHz for SerDes mode.
Instead of defining the PCIe/USB3 constants relative to SerDes
constants, define them with absolute values, thus making it a little bit
more obvious that different modes have different value tables.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I50c66c6bbe22b9a9bec4685600cb8560524a643c
The MODE_REFDIV constant is only used as mask of the MODE_REFDIV
register, but we already have MODE_REFDIV_MASK constant for that.
Drop MODE_REFDIV.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Icabb32189a7ca1a857dcf86cf0846bd0335f75d0
Constants SD_SPEED_1_25_G and SD_SPEED_2_5_G refer to SerDes frequency,
which is 1.25x that of data rate, since 1000base-x and 2500base-x use
the 8b/10b encoding:
mode frequency data rate
1000base-x 1.25 GHz 1 Gbps
2500base-x 3.125 GHz 2.5 Gbps
But the first constant refers to the frequency, while the second to the
data rate, which does not make sense.
Since the values in the specification refer to frequency, change the
name of the constant SD_SPEED_2_5_G to SD_SPEED_3_125_G to also refer to
the frequency, as SD_SPEED_1_25_G does.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I7670b45fa685aff93b3cafd84cf30d93620d8da1
According to Functional Specification, the common PHY register at offset
0x3f is actually Generation 3 Setting 2, while the register at offset
0x112 is Generation 2 Setting 3.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I4626672cbee2d08da1da7839a3cf3f90e78fa101
According to Functional Specification, the register at bit 1 of PHY
Configuration 1 is called PIN_PU_IVREF, not PIN_PU_IVEREF. Fix this.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I912fa4a1956bf0b1b35a24925db03e3dbbe1adf3
When tf-a is built with the llvm toolchain, the compiler optimizes the
variable in some way which results in SCMI_MSG_GET_TOKEN assert failure
in multiple places. This patch makes the msg_header variable in
mailbox_mem struct volatile, which seems to fix the issue.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I1d28b30a6472fc23ed85adff9cf73dfb536e39cc
It doesn't look correct to use mbed TLS defines directly in the Event
Log driver as this driver may use another Crypto library in future.
Hence mbed TLS Crypto dependency on Event Log driver is removed by
introducing generic Crypto defines and uses those in the Event Log
driver to call Crypto functions.
Also, updated mbed TLS glue layer to map these generic Crypto defines
to mbed TLS library defines.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ibc9c751f60cbce4d3f3cf049b7c53b3d05cc6735
As mpidr is unsigned long long, U should be ULL. We use macro to
fix this issue.
Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: I7dfd51a63f27f471794bcbf72ffff0c1a0598b46
Add a UART/USART driver for STM32 with complete a hardware support;
it used for STM32CubeProgrammer support with even parity.
This driver is not used for console, which is already handle
by a simple driver (drivers/st/uart/aarch32/stm32_console.S).
Change-Id: Ia9266e5d177fe7fd09c8a15b81da1a05b1bc8b2d
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
The PLL4 can be used by ROM code as the source clock of USB PHYC and,
in this case, the PLL4 configuration must be preserved
with pll4_preserve to avoid USB disturbance.
This patch also adds an error when the clock tree PLL4 configuration
is not the PLL4 configuration used by ROM code; this error allows to
detect a invalid clock tree.
This commit corrects the coverity issue 343023.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I4bae9312a2db8dd342a38e649513d689b13976bb
Sometimes when changing UART clock from TBG to XTAL, UART HW enters into
some broken state. It does not transit characters from TX FIFO anymore
and TX FIFO stays always empty. TX FIFO reset does not recover UART HW
from this broken state.
Experiments show that external reset can fix UART HW from this broken
state.
TF-A fatal error handler calls console_a3700_core_init() function to
initialize UART HW. This handler may be called anytime during CPU
runtime, also when kernel is running.
U-Boot or Linux kernel may change UART clock to TBG to achieve higher
baudrates. During initialization, console_a3700_core_init() resets UART
configuration to default settings, which means that it also changes
UART clock from TBG to XTAL.
Do an external reset of UART via North Bridge Peripheral reset register
to prevent this UART hangup.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8990bce24d1a6fd8ccc47a2cd0a5ff932fcfcf14
If TX FIFO is not empty, do not touch UART settings and let UART HW
transmit remaining bytes from TX FIFO. New UART settings are then set
only after TX FIFO is reset.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2976c0a4fbb841d3a79d42ef67c06e70174afc3b
Followup changes will need function arguments in registers x0, x1 and
x2. Do not modify x1 and x2 registers and instead use scratch x3 and x4
registers for storing local variables.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8551a802995f39128d2f4a8f8076b5bf463d0db0
Renamed a macro 'INVALID_ID' to 'EVLOG_INVALID_ID' to avoid its clash
with other macro names and to show it is explicitly used for Event
Log driver.
Change-Id: Ie4c92b3cd1366d9a59cd6f43221e24734865f427
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
The previous codes were using the cntpct_el0 to check the time
elapsed. But this physical timer does not seem to count for
the expected time resulting in gic fmu communication failures
on Tegra platforms.
This patch uses the delay_timer instead to use a platform
defined timer for calculating timeouts.
Change-Id: Ic8646ad1662c9928ac64c4152deb27e8c86fe344
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
sha 4ce3e99a3 introduced printf format specifiers for fixed width
types, which uses PRI*64 instead of "ll" for 64 bit values.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ic6811cc1788c698adde0807e5f8ab5290a900a26
Use long instead of long long on aarch64 for 64_t stdint types.
Introduce inttypes.h to properly support printf format specifiers for
fixed width types for such change.
Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
* changes:
feat(arm_fpga): write UART baud base clock frequency into DTB
feat(arm_fpga): query PL011 to learn system frequency
refactor(arm_fpga): move command line code into separate function
fix(fdt): avoid output on missing DT property
feat(arm_fpga): add ITS autodetection
feat(arm_fpga): determine GICR base by probing
feat(gicv3): introduce GIC component identification
feat(libfdt): also allow changing base address
fix(arm_fpga): avoid re-linking from executable ELF file
Correctly handle USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION request
in USB driver and support a different result than
USB_DESC_TYPE_CONFIGURATION with the new optional ops
get_other_speed_config_desc().
The support of this descriptor is optionnal and is only
required when high-speed capable device which can operate at its
other possible speed.
This patch allows to remove the pbuf update in usb_core_get_desc()
and solves an issue on USB re-enumeration on STM32MP15 platform
as the result of get_config_desc() is a const array.
This issue is not see on normal use-case, as the USB enumeration
is only done in ROM code and TF-A reuse the same USB descritors.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I8edcc1e45065ab4e45d48f4bc37b49120674fdb0
Remove the unnecessary cast on the result of function which
already return the correct type.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie21f7e78a880d30d1f31e32b3d2c3fb09489d65b
The GIC specification describes ID registers in each GIC register frame
(PIDRx), which can be used to identify a GIC component. The Arm Ltd. GIC
implementations use certain ID values to identify the distributor, the
redistributors and other parts like ITSes.
Introduce a function that reads those part number IDs, which are spread
over two registers. The actual numbers are only meaningful in connection
with a certain GIC model, which would need to be checked beforehand, by
the caller.
Change-Id: Ia6ff326a1e8b12664e4637bc8e2683d2b5c7721c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
CID 373791: Control flow issues (DEADCODE)
CID 373789: Control flow issues (DEADCODE)
Since USBD_EP_NB = 1 for DFU stack on STMP32MP15 platform (only EP0 is
required for DFU support) the value of num can't be different of 0
and the code can't be reached in usb_core_receive / usb_core_transmit.
Add a simple sub-function with this part of code.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I07a56909bb1e6de19ce52da7945b6d2916be8538
Correct the invalid test on NULL pointer pdev->class in
usb_core_set_config function.
This patch fix the coverity errors:
** CID 373790: Null pointer dereferences (FORWARD_NULL)
/drivers/usb/usb_device.c: 182 in usb_core_set_config()
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I83e43261bafa2d47f800e56df0b047a6c58a1e29
Add a device driver for Synopsis DWC2 USB IP of STM32MP15x,
this USB OTG device is only supported in device mode.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I90b21f094f6637b85f3ace23a3a3a2f6fd4e0951
Add a new USB framework to manage an USB device profile (USBD)
based on a peripheral controller driver (PCD).
This USB stack can be use to implement any Universal Serial Bus Device
Class in TF-A on top of a USB driver defined in the platform.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I7971ec6d952edec3511157a198e6e5359df4346b
there are features which are marked as experimental even though they
are stable and used for quite some time.
Following features are no longer marked as experimental
- SPMD
- MEASURED_BOOT
- FCONF and associated build flags
- DECRYPTION_SUPPORT and associated build flags
- ENABLE_PAUTH
- ENABLE_BTI
- USE_SPINLOCK_CAS
- GICv3 Multichip support
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I4bb653d9c413c66095ec31f0b8aefeb13ea04ee9
Currently the SCMI driver reports:
INFO: Initializing driver on Channel 0
on the console, which is not very specific (which driver?).
Add "SCMI" to the message so the user knows what the firmware is trying
to initialise.
Change-Id: Id8202655d07b8e12fe07670d462c6202e6eae2f0
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* changes:
feat(plat/rcar): change process for Suspend To RAM
fix(plat/rcar): change process that copy code to system ram
fix(plat/rcar): fix cache maintenance process of reading cert header
fix(plat/rcar): fix to load image when option BL2_DCACHE_ENABLE is enabled
Change processing of invalidate instruction cache to after changing
the RAM attribute.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # squash with rcar_gen3: drivers: Disable data cache while Suspend To RAM
Change-Id: I61339fc5415b26074b1e0753da4c4a432e8f83d9