RD-E1-Edge platform consists of two clusters with eight CPUs each and
two processing elements (PE) per CPU. Commit a9fbf13e04 (plat/arm/sgi:
move topology information to board folder) defined the RD-E1-Edge
topology tree to have two clusters with eight CPUs each but PE per CPU
entries were not added. This patch fixes the topology tree accordingly.
Change-Id: I7f97f0013be60e5d51c214fce3962e246bae8a0b
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
In preparation for adding support for Reference Design platforms
which have different base addresses for GIC Distributor or
Redistributor, move GIC related base addresses to individual platform
definition files.
Change-Id: Iecf52b4392a30b86905e1cd047c0ff87d59d0191
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Introduce macro 'CSS_SGI_CHIP_COUNT' to allow Arm CSS platforms with
multi-chip support to define number of chiplets on the platform. By
default, this flag is set to 1 and does not affect the existing single
chip platforms.
For multi-chip platforms, override the default value of
CSS_SGI_CHIP_COUNT with the number of chiplets supported on the
platform. As an example, the command below sets the number of chiplets
to two on the RD-N1-Edge multi-chip platform:
export CROSS_COMPILE=<path-to-cross-compiler>
make PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ARCH=aarch64 all
Change-Id: If364dc36bd34b30cc356f74b3e97633933e6c8ee
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Include multi-chip-mode parameter in HW_CONFIG dts to let next stage of
boot firmware know about the multi-chip operation mode.
Change-Id: Ic7535c2280fd57180ad14aa0ae277cf0c4d1337b
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
RD-N1-Edge based platforms can operate in dual-chip configuration
wherein two rdn1edge SoCs are connected through a high speed coherent
CCIX link.
This patch adds a function to check if the RD-N1-Edge platform is
operating in multi-chip mode by reading the SID register's NODE_ID
value. If operating in multi-chip mode, initialize GIC-600 multi-chip
operation by overriding the default GICR frames with array of GICR
frames and setting the chip 0 as routing table owner.
The address space of the second RD-N1-Edge chip (chip 1) starts from the
address 4TB. So increase the physical and virtual address space size to
43 bits to accommodate the multi-chip configuration. If the multi-chip
mode configuration is detected, dynamically add mmap entry for the
peripherals memory region of the second RD-N1-Edge SoC. This is required
to let the BL31 platform setup stage to configure the devices in the
second chip.
PLATFORM_CORE_COUNT macro is set to be multiple of CSS_SGI_CHIP_COUNT
and topology changes are added to represent the dual-chip configuration.
In order the build the dual-chip platform, CSS_SGI_CHIP_COUNT macro
should be set to 2:
export CROSS_COMPILE=<path-to-cross-compiler>
make PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ARCH=aarch64 all
Change-Id: I576cdaf71f0b0e41b9a9181fa4feb7091f8c7bb4
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
On systems that have multiple platform components that can interpret the
SCMI messages, there is a need to support multiple SCMI channels (one
each to those platform components). Extend the existing SCMI interface
that currently supports only a single SCMI channel to support multiple
SCMI channels.
Change-Id: Ice4062475b903aef3b5e5bc37df364c9778a62c5
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
In order to allow the MHUv2 driver to be usable with multiple MHUv2
controllers, use the base address of the controller from the platform
information instead of the MHUV2_BASE_ADDR macro.
Change-Id: I4dbab87b929fb0568935e6c8b339ce67937f8cd1
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
AFF3 bits of MPIDR corresponds to Chip-Id in Arm multi-chip platforms.
For calculating linear core position of CPU cores from slave chips, AFF3
bits has to be used. Update `plat_arm_calc_core_pos` assembly function
to include AFF3 bits in calculation.
Change-Id: I4af2bd82ab8e31e18bc61de22705a73893954260
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Some of the Reference Design platforms like RD-N1-Edge can operate in
multi-chip configuration wherein two or more SoCs are connected through
a high speed coherent CCIX link. For the RD platforms, the remote chip
address space is at the offset of 4TB per chip. In order for the primary
chip to access the device memory region on the remote chip, the required
memory region entries need to be added as mmap entry. This patch adds
macros related to the remote chip device memory region.
Change-Id: I833810b96f1a0e7c3c289ac32597b6ba03344c80
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Multi-chip platforms have two or more identical chips connected using a
high speed coherent link. In order to identify such platforms,
add chip_id and multi_chip_mode information in the platform variant
info structure. The values of these two new elements is populated
during boot.
Change-Id: Ie6e89cb33b3f0f408814f6239cd06647053e23ed
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
For SGI-575 and RD platforms, move bl31_platform_setup handler to
individual board files to allow the platforms to perform board specific
bl31 setup.
Change-Id: Ia44bccc0a7f40a155b33909bcb438a0909b20d42
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Currently, an IO setup failure will be ignored on arm platform release
build. Change this to panic instead.
Change-Id: I027a045bce2422b0a0fc4ff9e9d4c6e7bf5d2f98
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Change the return type of "arm_io_is_toc_valid()" and
"plat_arm_bl1_fwu_needed()" to bool, to match function behavior.
Change-Id: I503fba211219a241cb263149ef36ca14e3362a1c
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Use the firmware configuration framework to store the io_policies
information inside the configuration device tree instead of the static
structure in the code base.
The io_policies required by BL1 can't be inside the dtb, as this one is
loaded by BL1, and only available at BL2.
This change currently only applies to FVP platform.
Change-Id: Ic9c1ac3931a4a136aa36f7f58f66d3764c1bfca1
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Use the firmware configuration framework in arm dynamic configuration
to retrieve mbedtls heap information between bl1 and bl2.
For this, a new fconf getter is added to expose the device tree base
address and size.
Change-Id: Ifa5ac9366ae100e2cdd1f4c8e85fc591b170f4b6
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Use fconf to retrieve the `disable_authentication` property.
Move this access from arm dynamic configuration to bl common.
Change-Id: Ibf184a5c6245d04839222f5457cf5e651f252b86
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
This patch introduces a better separation between the trusted-boot
related properties, and the dynamic configuration DTBs loading
information.
The dynamic configuration DTBs properties are moved to a new node:
`dtb-registry`. All the sub-nodes present will be provided to the
dynamic config framework to be loaded. The node currently only contains
the already defined configuration DTBs, but can be extended for future
features if necessary.
The dynamic config framework is modified to use the abstraction provided
by the fconf framework, instead of directly accessing the DTBs.
The trusted-boot properties are kept under the "arm,tb_fw" compatible
string, but in a separate `tb_fw-config` node.
The `tb_fw-config` property of the `dtb-registry` node simply points
to the load address of `fw_config`, as the `tb_fw-config` is currently
part of the same DTB.
Change-Id: Iceb6c4c2cb92b692b6e28dbdc9fb060f1c46de82
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Use the dtb provided by bl1 as configuration file for fconf.
Change-Id: I3f466ad9b7047e1a361d94e71ac6d693e31496d9
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Move the loading of the dtb from arm_dym_cfg to fconf. The new loading
function is not associated to arm platform anymore, and can be moved
to bl_main if wanted.
Change-Id: I847d07eaba36d31d9d3ed9eba8e58666ea1ba563
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Introduce the Firmware CONfiguration Framework (fconf).
The fconf is an abstraction layer for platform specific data, allowing
a "property" to be queried and a value retrieved without the requesting
entity knowing what backing store is being used to hold the data.
The default backing store used is C structure. If another backing store
has to be used, the platform integrator needs to provide a "populate()"
function to fill the corresponding C structure.
The "populate()" function must be registered to the fconf framework with
the "FCONF_REGISTER_POPULATOR()". This ensures that the function would
be called inside the "fconf_populate()" function.
A two level macro is used as getter:
- the first macro takes 3 parameters and converts it to a function
call: FCONF_GET_PROPERTY(a,b,c) -> a__b_getter(c).
- the second level defines a__b_getter(c) to the matching C structure,
variable, array, function, etc..
Ex: Get a Chain of trust property:
1) FCONF_GET_PROPERY(tbbr, cot, BL2_id) -> tbbr__cot_getter(BL2_id)
2) tbbr__cot_getter(BL2_id) -> cot_desc_ptr[BL2_id]
Change-Id: Id394001353ed295bc680c3f543af0cf8da549469
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Commit 8f73663b59 ("plat/arm: Support for Cortex A5 in FVP Versatile
Express platform") has conditioned the enabling of the Advanced SIMD
and floating point features to platforms that have:
(ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_VFP)
QEMU does support VFP so it should set ARMV7_SUPPORTS_VFP.
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Change-Id: I3bab7c2ed04766d0628c14094557b2751f60a428
This patch modify current address range checker in SiP driver to also
accept input size.
Also, include said checker for SiP mailbox send command to ensure
referenced argument is within expected address.
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ie0c3cac4c3d1a6ea0194602d9aa3541f5d9a3367
Enables usage of ARM_ROTPK_LOCATION=regs for FVP board.
Removes hard-coded developer keys. Instead, setting
ARM_ROTPK_LOCATION=devel_* takes keys from default directory.
In case of ROT_KEY specified - generates a new hash and replaces the
original.
Note: Juno board was tested by original feature author and was not tested
for this patch since we don't have access to the private key. Juno
implementation was moved to board-specific file without changing
functionality. It is not known whether byte-swapping is still needed
for this platform.
Change-Id: I0fdbaca0415cdcd78f3a388551c2e478c01ed986
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Stack usage reaches 90% with some configuration. Bump slightly the stack
size to prevent a stack-overflow.
Change-Id: I44ce8b12906586a42f152b7677785fcdc5e78ae1
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
BL2 is unconditionally setting 0 (OPTEE_AARCH64) in arg0 even when the
BL32 image is 32bit (OPTEE_AARCH32). This is causing the boot to hang
when ATOS (32bit Amlogic BL32 binary-only TEE OS) is used.
Since we are not aware of any Amlogic platform shipping a 64bit version
of ATOS we can hardcode OPTEE_AARCH32 / MODE_RW_32 when using ATOS.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Iaea47cf6dc48bf8a646056761f02fb81b41c78a3
Introduce the preliminary support for the Amlogic A113D (AXG) SoC.
This port is a minimal implementation of BL31 capable of booting
mainline U-Boot, Linux and chainloading BL32 (ATOS).
Tested on a A113D board.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ic4548fa2f7c48d61b485b2a6517ec36c53c20809
Fix code that violates the MISRA rule:
MISRA C-2012 Rule 11.9: Literal "0" shall not be used as
null pointer constant.
The fix explicitly checks whether a pointer is NULL.
Change-Id: Ibc318dc0f464982be9a34783f24ccd1d44800551
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
This patch adds the nvg_roc_clean_cache_trbits() function prototype
to mce_private.h to fix compilation failures seen with the Tegra194
builds.
Change-Id: I313556f6799792fc0141afb5822cc157db80bc47
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This update allows normal world to send mailbox commands through SMC
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I587bea06422da90e5907d586495cd9e3bde900f6
Introduce support for RSU that can be initiated through SMC calls.
Added features as below:
- RSU status
- RSU update
- RSU HPS notify
- RSU get sub-partition
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I78d5a07688e43da99f03d77dfd45ffb4a78f2e4c
This patch adds 'fdtw_read_bytes' and 'fdtw_write_inplace_bytes'
functions for read/write array of bytes from/to a given property.
It also adds 'fdt_setprop_inplace_namelen_partial' to jmptbl.i
files for builds with USE_ROMLIB=1 option.
Change-Id: Ied7b5c8b38a0e21d508aa7bcf5893e656028b14d
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Platform handoff structure no longer includes boot source selection.
Hence, those settings can now be configured through socfpga_plat_def.h.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: If7ec6a03bb25156a6670ebf8f77105c370b553f6
Tegra186 is in production so lock stream id security configs
for all the clients.
Change-Id: I64bdd5a9f12319a543291bfdbbfc1559d7a44113
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
This patch removes support for simulated system suspend for Tegra194
platforms as we have actual silicon platforms that support this
feature now.
Change-Id: I9ed1b002886fed7bbc3d890a82d6cad67e900bae
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch fixes violations of the following MISRA rules
* Rule 8.5 "An external object or function shall be declared once in
one and only one file"
* Rule 10.3 "The value of an expression shall not be assigned to an
object with a narrower essential type or of a different
esential type category"
Change-Id: I4314cd4fea0a4adc6665868dd31e619b4f367e14
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch fixes violations for the following MISRA rules
* Rule 5.7 "A tag name shall be a unique identifier"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.3 "The value of an expression shall not be assigned to an object
with a narrower essential type or of a different essential type
category"
* Rule 10.4 "Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential type
category"
* Rule 20.7 "Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses"
* Rule 21.1 "#define and #undef shall not be used on a reserved identifier
or reserved macro name"
Change-Id: I83cbe659c2d72e76dd4759959870b57c58adafdf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch fixes violations for the following MISRA rules
* Rule 8.4 "A compatible declaration shall be visible when an object or
function with external linkage is defined"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.6 "Both operands of an operator in which the usual arithmetic
conversions are perdormed shall have the same essential type
category"
* Rule 17.7 "The value returned by a function having non-void return
type shall be used"
Change-Id: I171ac8340de729fd7be928fa0c0694e9bb8569f0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
The PMC driver is used only by Tegra210 and Tegra132 platforms. This
patch removes pmc.c from the common makefile and moves it to the
platform specific makefiles.
As a result, the PMC code from common code has been moved to Tegra132
and Tegra210 platform ports.
Change-Id: Ia157f70e776b3eff3c12eb8f0f02d30102670a98
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch removes the per-platform, weakly defined TZDRAM setup handler,
as all affected platforms implement the actual handler.
Change-Id: I95d04b2a771bc5d673e56b097d45c493fa388ee8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch removes the weakly defined per-platform SiP handler
as all platforms implement this handler, defeating the need for
a weak definition.
Change-Id: Id4c7e69163d2635de1813f5a385ac874253a8da9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.
Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch converts the weakly defined platform setup handlers into
actual platform specific handlers to improve code coverage numbers
and some MISRA defects.
The weakly defined handlers never get executed thus resulting in
lower coverage - function, function calls, statements, branches
and pairs.
Change-Id: I02f450f66b5754a90d934df4d76eb91459fca5f9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Tegra194 supports upto 64GB of DRAM, whereas the previous SoCs support
upto 32GB DRAM. This patch moves the common DRAM base/end macros to
individual Tegra SoC headers to fix this anomaly.
Change-Id: I1a9f386b67c2311baab289e726d95cef6954071b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Extend possible images to 8, additionaly add another type which will be
used with platform containing up to 3 CPs.
Change-Id: Ib68092d11af9801e344d02de839f53127e056e46
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
In order to access MG SRAM, the amb bridge needs to be configured which is
done in bl2 platform init.
For MG CM3, the image is only loaded to its SRAM and the CM3 itself is
left in reset. It is because the next stage bootloader (e.g. u-boot)
will trigger action which will take it out of reset when needed. This
can happen e.g. when appropriate device-tree setup (which has enabled
802.3 auto-neg) will be chosen. In other cases the MG CM3 should not be
running.
Change-Id: I816ea14e3a7174eace068ec44e3cc09998d0337e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
pm_get_callbackdata() expect result count and not total bytes of
result. Correct it by passing result count to pm_get_callbackdata().
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I01ce0002f7a753e81ea9fe65edde8420a13ed51a
To find result count use ARRAY_SIZE for better readability.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I97201de4d43024e59fa78bd61937c86d47724ab5
Allows to select the chain of trust to use when the Trusted Boot feature
is enabled. This affects both the cert_create tool and the firmware
itself.
Right now, the only available CoT is TBBR.
Change-Id: I7ab54e66508a1416cb3fcd3dfb0f055696763b3d
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
This patch enables uboot's spl entrypoint to BL31 and also handles
secondary cpus state during cold boot.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib70ec91a3ad09a568cb66e7c1e23a2b3e460746c
This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.
Consequently, this patch also fixes the issues reported by this
flag. Consider the following two lines of code from two different source
files(bl_common.h and bl31_plat_setup.c):
IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE);
The IMPORT_SYM macro which actually imports a linker symbol as a C expression.
The macro defines the __RO_START__ as an extern variable twice, one for each
instance. __RO_START__ symbol is defined by the linker script to mark the start
of the Read-Only area of the memory map.
Essentially, the platform code redefines the linker symbol with a different
(relevant) name rather than using the standard symbol. A simple solution to
fix this issue in the platform code for redundant declarations warning is
to remove the second IMPORT_SYM and replace it with following assignment
static const unsigned long BL2_RO_BASE = BL_CODE_BASE;
Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* changes:
ti: k3: drivers: ti_sci: Put sequence number in coherent memory
ti: k3: drivers: ti_sci: Remove indirect structure of const data
ti: k3: common: Enable ARM cluster power down
ti: k3: common: Rename device IDs to be more consistent
This patch enables the config to switch to the console provided
by the SPE firmware.
Change-Id: I5a3bed09ee1e84f958d0925501d1a79fb7f694de
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate
the build to require that ARM_BL31_IN_DRAM is enabled as well.
Naturally with SEPARATE_NOBITS_REGION enabled, the BL31 initialization code
cannot be reclaimed to be used for runtime data such as secondary cpu stacks.
Memory map for BL31 NOBITS region also has to be created.
Change-Id: Ibbc8c9499a32e63fd0957a6e254608fbf6fa90c9
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
The current message sequence number is accessed both with caches on and
off so put this memory in the un-cached coherent section so accesses
are consistent and coherency is maintained.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ieeefefeaffc691e4e4c4de7c74490d50ff9de807
The 'info' structure contained what is only static data for this
implementation of TI-SCI. Remove this indirection and remove the
struct.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I2328fddf388bf7d56a56bd673c080e78c86fe072
When all cores in a cluster are powered down the parent cluster can
be also powered down. When the last core has requested powering down
follow by sending the cluster power down sequence to the system
power controller firmware.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I0ffeb339852c66ef62743aecd3e17ca20bad6216
The core number is called 'core_id' but the processor and device IDs are
called 'proc' and 'device'. Rename these to make them less confusing.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I3d7c6dddd7aa37b5dee1aa9689ce31730e9c3b59
* changes:
uniphier: make all BL images completely position-independent
uniphier: make uniphier_mmap_setup() work with PIE
uniphier: pass SCP base address as a function parameter
uniphier: set buffer offset and length for io_block dynamically
uniphier: use more mmap_add_dynamic_region() for loading images
bl_common: add BL_END macro
uniphier: turn on ENABLE_PIE
TSP: add PIE support
BL2_AT_EL3: add PIE support
BL31: discard .dynsym .dynstr .hash sections to make ENABLE_PIE work
PIE: pass PIE options only to BL31
Build: support per-BL LDFLAGS
The platform topology description of the upcoming Arm's RD platforms
have different topology than those listed in the sgi_topology.c file. So
instead of adding platform specific topology into existing
sgi_topology.c file, those can be added to respective board files. In
order to maintain consistency with the upcoming platforms, move the
existing platform topology description to respective board files.
Change-Id: I4689c7d24cd0c75a3dc234370c34a85c08598abb
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
As on SGI platforms, SCPI is unsupported on SGM platforms.
Change-Id: I556ed095b9eb55b72447230ee2725d3c76160a08
Signed-off-by: Chris Kay <chris.kay@arm.com>
This platform supports multiple SoCs. The next SoC will still keep
quite similar architecture, but the memory base will be changed.
The ENABLE_PIE improves the maintainability and usability. You can reuse
a single set of BL images for other SoC/board without re-compiling TF-A
at all. This will also keep the code cleaner because it avoids #ifdef
around various base addresses.
By defining ENABLE_PIE, BL2_AT_EL3, BL31, and BL32 (TSP) are really
position-independent now. You can load them anywhere irrespective of
their link address.
Change-Id: I8d5e3124ee30012f5b3bfa278b0baff8efd2fff7
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
BL2_BASE, BL31_BASE, and BL32_BASE are defined in platform_def.h,
that is, determined at link-time.
On the other hand, BL2_END, BL31_END, and BL32_END are derived from
the symbols produced by the linker scripts. So, they are fixed-up
at run-time if ENABLE_PIE is enabled.
To make it work in a position-indepenent manner, use BL_CODE_BASE and
BL_END, both of which are relocatable.
Change-Id: Ic179a7c60eb64c5f3024b178690b3ac7cbd7521b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, UNIPHIER_SCP_BASE is hard-coded in uniphier_scp_start(),
which is not handy for PIE.
Towards the goal of making this really position-independent, pass in
image_info->image_base.
Change-Id: I88e020a1919c607b1d5ce70b116201d95773bb63
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, the .buffer field in io_block_dev_spec is statically set,
which is not handy for PIE.
Towards the goal of making this really position-independent, set the
buffer length and length in the uniphier_io_block_setup() function.
Change-Id: I22b20d7b58d6ffd38f64f967a2820fca4bd7dade
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, uniphier_bl2_mmap hard-codes the memory region needed for
loading other images.
Towards the goal of making this really position-independent, call
mmap_add_dynamic_region() before that region gets accessed.
Change-Id: Ieb505b91ccf2483e5f1a280accda564b33f19f11
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now that various issues in the PIE support have been fixed,
this platform can enable ENABLE_PIE.
I tested BL2_AT_EL3, BL31, TSP, and all of them worked.
Change-Id: Ibc499c6bad30b7f81a42bfa7e435ce25f820bd9c
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* changes:
Tegra194: mce: remove unused NVG functions
Tegra194: support for NVG interface v6.6
Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list
Tegra194: enable driver for general purpose DMA engine
Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms
Tegra194: organize the memory/mmio map to make it linear
Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1
Tegra194: support for boot params wider than 32-bits
Tegra194: memctrl: set reorder depth limit for PCIE blocks
Tegra194: memctrl: program MC_TXN_OVERRIDE reg for PTCR, MPCORE and MIU
Tegra194: memctrl: set CGID_TAG_ADR instead of CGID_TAG_DEFAULT
Tegra194: memctrl: update mss reprogramming as HW PROD settings
Tegra194: memctrl: Disable PVARDC coalescer
Tegra194: memctrl: force seswr/rd transactions as passsthru & coherent
Tegra194: Request CG7 from last core in cluster
Tegra194: toggle SE clock during context save/restore
Tegra: bpmp: fix header file paths
* changes:
intel: Add function to check fpga readiness
intel: Add bridge control for FPGA reconfig
intel: FPGA config_isdone() status query
intel: System Manager refactoring
intel: Refactor reset manager driver
intel: Enable bridge access in Intel platform
intel: Modify non secure access function
PCIE0R1 security and override registers need to be preserved across
system suspend. Adding them to system suspend save register list.
Due to addition of above registers, increasing context save memory
by 2 bytes.
Change-Id: I1b3a56aee31f3c11e3edc2fb0a6da146eec1a30d
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
This patch enables the GPCDMA for all Tegra194 platforms to help
accelerate all the memory copy operations.
Change-Id: I8cbec99be6ebe4da74221245668b321ba9693479
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Many simulation/emulation platforms do not support this hardware block
leading to SErrors during register accesses.
This patch conditionally accesses the registers from this block only
on actual Si and FPGA platforms.
Change-Id: Ic22817a8c9f81978ba88c5362bfd734a0040d35d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch organizes the platform memory/mmio map, so that the base
addresses for the apertures line up in ascending order. This makes
it easier for the xlat_tables_v2 library to create mappings for each
mmap_add_region call.
Change-Id: Ie1938ba043820625c9fea904009a3d2ccd29f7b3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
PCIE0R1 does not program stream IDs, so allow the stream ID to be
overriden by the MC.
Change-Id: I4dbd71e1ce24b11e646de421ef68c762818c2667
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
The previous bootloader is not able to pass boot params wider than
32-bits due to an oversight in the scratch register being used. A
new secure scratch register #75 has been assigned to pass the higher
bits.
This patch adds support to parse the higher bits from scratch #75
and use them in calculating the base address for the location of
the boot params.
Scratch #75 format
====================
31:16 - bl31_plat_params high address
15:0 - bl31_params high address
Change-Id: Id53c45f70a9cb370c776ed7c82ad3f2258576a80
Signed-off-by: Steven Kao <skao@nvidia.com>
HW bug in third party PCIE IP - PCIE datapath hangs when there are
more than 28 outstanding requests on data backbone for x1 controller.
Suggested SW WAR is to limit reorder_depth_limit to 16 for
PCIE 1W/2AW/3W clients.
Change-Id: Id5448251c35d2a93f66a8b5835ae4044f5cef067
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
-PTCR is ISO client so setting it to FORCE_NON_COHERENT.
-MPCORER, MPCOREW and MIU0R/W to MIU7R/W clients itself will provide
ordering so no need to override from mc.
-MIU0R/W to MIU7R/W clients registers are not implemented in tegrasim
so skipping it for simulation.
-All the clients need to set CGID_TAG_ADR to maintain request ordering
within a 4K boundary.
Change-Id: Iaa3189a1f3e40fb4cef28be36bc4baeb5ac8f9ca
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
- All SoC clients should use CGID_TAG_ADR to improve perf
- Remove tegra194_txn_override_cfgs array that is not getting used.
Change-Id: I9130ef5ae8659ed5f9d843ab9a0ecf58b5ce9c74
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Memory clients are divided in to ISO/NonISO/Order/Unordered/Low
BW/High BW. Based on the client types, HW team recommends, different
memory ordering settings, IO coherency settings and SMMU register settings
for optimized performance of the MC clients.
For example ordered ISO clients should be set as strongly ordered and
should bypass SCF and directly access MC hence set as
FORCE_NON_COHERENT. Like this there are multiple recommendations
for all of the MC clients.
This change sets all these MC registers as per HW spec file.
Change-Id: I8a8a0887cd86bf6fe8ac7835df6c888855738cd9
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Due to a hardware bug PVA may perform memory transactions which
cause coalescer faults. This change works around the issue by
disabling coalescer for PVA0RDC and PVA1RDC.
Change-Id: I27d1f6e7bc819fb303dae98079d9277fa346a1d3
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Force memory transactions from seswr and sesrd as coherent_snoop from
no-override. This is necessary as niso clients should use coherent
path.
Presently its set as FORCE_COHERENT_SNOOP. Once SE+TZ is enabled
with SMMU, this needs to be replaced by FORCE_COHERENT.
Change-Id: I8b50722de743b9028129b4715769ef93deab73b5
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
- SC7 requires all the cluster groups to be in CG7 state, else
is_sc7_allowed will get denied
- As a WAR while requesting CC6, request CG7 as well
- CG7 request will not be honored if it is not last core in Cluster
group
- This is just to satisfy MCE for now as CG7 is going to be defeatured
Change-Id: Ibf2f8a365a2e46bd427abd563da772b6b618350f
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
This patch adds support to toggle SE clock, using the bpmp_ipc
interface, to enable SE context save/restore. The SE sequence mostly
gets called during System Suspend/Resume.
Change-Id: I9cee12a9e14861d5e3c8c4f18b4d7f898b6ebfa7
Signed-off-by: steven kao <skao@nvidia.com>
This patch fixes the header file paths to include debug.h
from the right location.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: If303792d2169158f436ae6aa5b6d7a4f88e28f7b
This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has
semihosting enabled, but that is already assumed by the image loader.
Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: I0fb7cf7909262b675c3143efeac07f4d60730b03
This lets the Linux kernel or any other image which expects an FDT in x0 be
loaded directly as BL33 without a separate bootloader on QEMU.
Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: Ia8eb4710a3d97cdd877af3b8aae36a2de7cfc654
Parse the parameter structure the PLM populates, to populate the
bl32 and bl33 image structures.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I317072d1086f6cc6f90883c1b8b6d086ff57b443
ATF handover can be used by Xilinx platforms, so move it to common
file from platform specific files.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I5f0839351f534619de581d1953c8427a079487e0
Even though ERET always causes a jump to another address, aarch64 CPUs
speculatively execute following instructions as if the ERET
instruction was not a jump instruction.
The speculative execution does not cross privilege-levels (to the jump
target as one would expect), but it continues on the kernel privilege
level as if the ERET instruction did not change the control flow -
thus execution anything that is accidentally linked after the ERET
instruction. Later, the results of this speculative execution are
always architecturally discarded, however they can leak data using
microarchitectural side channels. This speculative execution is very
reliable (seems to be unconditional) and it manages to complete even
relatively performance-heavy operations (e.g. multiple dependent
fetches from uncached memory).
This was fixed in Linux, FreeBSD, OpenBSD and Optee OS:
679db7080129fb48ace43a08873eceabfd092aa1
It is demonstrated in a SafeSide example:
https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cchttps://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c
Signed-off-by: Anthony Steinhauser <asteinhauser@google.com>
Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
* changes:
plat: xilinx: Move pm_client.h to common directory
plat: xilinx: versal: Make silicon default build target
xilinx: versal: Wire silicon default setup
versal: Increase OCM memory size for DEBUG builds
plat: xilinx: versal: Dont set IOU switch clock
arm64: versal: Adjust cpu clock for versal virtual
xilinx: versal: Add support for PM_GET_OPERATING_CHARACTERISTIC EEMI call
plat: versal: Add Get_ChipID API
plat: xilinx: versal: Add load Pdi API support
xilinx: versal: Add feature check API
xilinx: versal: Implement set wakeup source for client
plat: xilinx: versal: Add GET_CALLBACK_DATA function
xilinx: versal: Add PSCI APIs for system shutdown & reset
xilinx: versal: Add PSCI APIs for suspend/resume
xilinx: versal: Remove no_pmc ops to ON power domain
xilinx: versal: Add set wakeup source API
xilinx: versal: Add client wakeup API
xilinx: versal: Add query data API
xilinx: versal: Add request wakeup API
xilinx: versal: Add PM_INIT_FINALIZE API for versal
xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API
xilinx: versal: enable ipi mailbox service
xilinx: move ipi mailbox svc to xilinx common
plat: xilinx: versal: Implement PM IOCTL API
xilinx: versal: Implement power down/restart related EEMI API
xilinx: versal: Add SMC handler for EEMI API
xilinx: versal: Implement PLL related PM APIs
xilinx: versal: Implement clock related PM APIs
xilinx: versal: Implement pin control related PM APIs
xilinx: versal: Implement reset related PM APIs
xilinx: versal: Implement device related PM APIs
xilinx: versal: Add support for suspend related APIs
xilinx: versal: Add get_api_version support
xilinx: Add support to send PM API to PMC using IPI for versal
plat: xilinx: versal: Move versal_def.h to include directory
plat: xilinx: versal: Move versal_private.h to include directory
plat: xilinx: zynqmp: Use GIC framework for warm restart
In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate
the build to require that ARM_BL31_IN_DRAM is enabled as well.
Naturally with SEPARATE_NOBITS_REGION enabled, the BL31 initialization code
cannot be reclaimed to be used for runtime data such as secondary cpu stacks.
Memory map for BL31 NOBITS region also has to be created.
Change-Id: Ibd480f82c1dc74e9cbb54eec07d7a8fecbf25433
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* changes:
Tegra194: platform handler for entering CPU standby state
Tegra194: memctrl: force viw and vifalr/w transactions as non-coherent
Tegra194: memctrl: fix bug in client order id reg value generation
Tegra194: memctrl: enable mc coalescer
Tegra194: update scratch registers used to read boot parameters
Tegra194: implement system shutdown/reset handlers
Tegra194: mce: support for shutdown and reboot
Tegra194: request CG7 before checking if SC7 is allowed
Tegra194: config to enable/disable strict checking mode
Tegra194: remove unused platform configs
Tegra194: restore XUSB stream IDs on System Resume
Remove the general BL31 mmap region: it duplicates the existing static
mapping for the entire SRAM region. Use the helper definitions when
applicable to simplify the code and add the MT_EXECUTE_NEVER flag.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I7a6b79e50e4b5c698774229530dd3d2a89e94a6d
STM32MP1 platform is able to boot from SPI-NOR devices.
These modifications add this support using the new
SPI-NOR framework.
Change-Id: I75ff9eba4661f9fb87ce24ced2bacbf8558ebe44
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
STM32MP1 platform is able to boot from SPI-NAND devices.
These modifications add this support using the new
SPI-NAND framework.
Change-Id: I0d5448bdc4bde153c1209e8043846c0f935ae5ba
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
STM32MP1 platform is able to boot from raw NAND devices.
These modifications add this support using the new
raw NAND framework.
Change-Id: I9e9c2b03930f98a5ac23f2b6b41945bef43e5043
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
For STM32MP1, the address space is 4GB, which can be first divided
in 4 parts of 1GB. This LVL1 table is already mapped regardless
of MAX_XLAT_TABLES.
Fixing typo: Replace Ko to KB.
BL2/sp_min for platform STM32MP1 requires 4 MMU translation tables:
- a level2 table and a level3 table for identity mapped SYSRAM
- a level2 table mapping 2MB of BootROM runtime resources
- a level2 table mapping 2MB of secure DDR (case BL32 is OP-TEE)
Change-Id: If80cbd4fccc7689b39dd540d6649b1313557f326
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Add a new entry to find register properties by name and
include new assert functions to limit address cells to 1
and size cells to 1.
Change-Id: Ide59a795a05fb2af36bd07fec15e5a3adf196226
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Adds compilation flags to specify which drivers will be
embedded in the generated firmware.
Change-Id: Ie9decc89c3f26cf17e7148a3a4cf337fd35940f7
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
* changes:
zynqmp: pm: clock: Move custom flags to typeflags
zynqmp: pm: clock: Add support for custom type flags
plat: xilinx: zynqmp: Add GET_CALLBACK_DATA function
zynqmp: pm: Remove CLK_TOPSW_LSBUS from invalid clock list
This patch implements a handler to enter the standby state on
Tegra194 platforms. On receiving a CPU_STANDBY state request,
the platform handler issues TEGRA_NVG_CORE_C6 request to the
MCE firmware to take the CPU into the standby state.
Change-Id: I703a96ec12205853ddb3c3871b23e338e1f60687
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Force memory transactions from viw and viflar/w as non-coherent from
no-override. This is necessary as iso clients shouldn't use coherent
path and stage-2 smmu mappings won't mark transactions as non-coherent.
For native case, no-override works. But, not for virtualization case.
Change-Id: I1a8fc17787c8d0f8579bdaeeb719084993e27276
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Client order id reset values are incorrectly and'ed with
mc_client_order_id macro, which resulted in getting reg value as
always zero. Updated mc_client_order_id macro to avoid and'ing outside
the macro, to take the reg value and update specific bit field
as necessary.
Change-Id: I880be6e4291d7cd58cf70d7c247a4044e57edd9e
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
This patch enable the Memory Controller's "Coalescer" feature to
improve performance of memory transactions.
Change-Id: I50ba0354116284f85d9e170c293ce77e9f3fb4d8
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
This patch changes SCRATCH_BOOT_PARAMS_ADDR macro to use SECURE_SCRATCH_RSV81
instead of SECURE_SCRATCH_RSV44. The previous level bootloader changed this
setting, so update here to keep both components in sync.
Change-Id: I4e0c1b54fc69482d5513a8608d0bf616677e1bdd
Signed-off-by: steven kao <skao@nvidia.com>
This patch implements the PSCI system shutdown and reset handlers,
that in turn issue the MCE commands.
Change-Id: Ia9c831674d7be615a6e336abca42f397e4455572
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
This patch adds support for shutdown/reboot handlers to the MCE
driver.
ATF communicates with mce using nvg interface for shutdown &
reboot. Both shutdown and reboot use the same nvg index.
However, the 1st bit of the nvg data argument differentiates
whether its a shutdown or reboot.
Change-Id: Id2d1b0c4fec55abf69b7f8adb65ca70bfa920e73
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
Currently firmware seems to be checking if we can get into system
suspend after checking if CC6 & C7 is allowed. For system suspend
to be triggered, the firmware needs to request for CG7 as well.
This patch fixes this anomaly.
Change-Id: I39c4c50092a4288f4f3fa4b0b1d5026be50f058f
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds a new configuration option to the platform makefiles
that disables/enables strict checking mode. The config is enabled
by default.
Change-Id: I727dd0facee88d9517bf6956eaf9163eba25c8bb
Signed-off-by: Steven Kao <skao@nvidia.com>
The stream IDs for XUSB programmed during cold boot are lost on System
Suspend. This patch restores the XUSB stream IDs on System Resume.
NOTE: THE WARMBOOT CODE NEEDS TO MAKE SURE THAT THE XUSB MODULE IS OUT
OF RESET AND THE CLOCKS ARE ENABLED, BEFORE POWERING ON THE CPU, DURING
SYSTEM RESUME.
Change-Id: Ibd5f1e5ebacffa6b29b625f4c41ecf204afa8191
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Create a function to check for fpga readiness, and move the checking out
of bridge enable function.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3f473ffeffa9ce181a48977560c8bda19c6123c0
This is to make sure that bridge access in disabled before doing full
FPGA reconfiguration and turn re-enable it once the configuration
succeed.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d
SiP CONFIG_ISDONE now will query status for either CONFIG_STATUS or
RECONFIG_STATUS based on passed parameter
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Idb8a84af4e98654759843de09a289d31246c9a91
Refactored system manager driver to be shared across both intel platform
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d
Refactor reset manager into intel common platform directory as it can be
shared by both Stratix 10 and Agilex. Register address and field is now
referred through macros.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a
Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f
Combine both peripheral and bridge non-secure access code
into a single callable function
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I38d335ed8d1e9f55d337b63cca121a473897ef70
Move pm_client.h to common directory to avoid duplication
of function declaration.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Iea542e681f42db089cccd9b24d286ac8f0a2ce35
This patch makes default build target as silicon instead of QEMU.
The default can be overwritten by specifying it through build flag
VERSAL_PLATFORM.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ia4cb1df1f206db3e514e8ce969acca875e973ace
Add new option for serial and default clock setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I0ca7ad51637cdaa6bb891f22c53595d20da7236a
ATF can't fit in current OCM size when the DEBUG is enabled, so
increase the OCM size to use 128Kb.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I2ebfd1f2e9db9c0b28770aea7f8fbf1a8a15787a
The IOU switch clock will be set by PLM during boot so there is no need to
set here and hence this patch removes it.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I1512708411eb07a07c1a8fbd66575efee975431a
This patch modifies cpu clock for Xilinx Versal virtual
platform in order to keep same as used by QEMU.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I169d082462d7ce94a82c62966ab9eb122c5a3fee
This patch adds EEMI support for PM_GET_OPERATING_CHARACTERISTIC api id. This
interface obtains operating characteristic of a device from PMC firmware. The
'power', 'temperature', and 'latency' characteristic are the options that are
supported.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: If30959ba6a3a778a17df2a4281c2c09832cf7e92
Add support for Get_ChipID API in Versal which calls corresponding
LibPM API.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I25c4b301721d7989d982ac376c59195c55564022
This patch adds support for load pdi api to enable loading
pdi from linux.
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I48549e276e1f7b9be45a0bebf559f73bd09d5f69
Add API to check availability of given API in ATF
as well as platform management controller and returns
the supported version number.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I608b38f60b36c4d105b7a205ecb8b02de0c00f3c
Add support to set wakeup source for APU while suspending.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I4809fd83a710def8144fdad74990c45e62b8fdf3
Add GET_CALLBACK_DATA function to get IPI callback
data in Linux during init suspend callback.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ieb60e561b5f656611f0702c43ba6a4296a012651
Add following APIs in plat_psci to support system shutdown & reset:
- versal_system_off
- versal_system_reset
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ia2c1a19ded18984b393e1fdee760bf48b45e9902
Add following APIs in plat_psci to support suspend resume:
- versal_pwr_domain_off
- versal_pwr_domain_suspend
- versal_pwr_domain_suspend_finish
- versal_validate_power_state
- versal_get_sys_suspend_power_state
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ife908a45f32e2037c9c19e13211a8e4b373b8342
Add PMC ops for power domain ON and remove no_pmc ops.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Id4308dfe124b60a751765beb3397d1b0071f14fc
Implement set wakeup source API to pass SMC
call for set wakeup source to PLM (Platform Loader
and Manager).
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I654ce07235c0fc7dfcb81bf98820153255f61537
Implement client wakeup API for versal.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I31b1b362fe645a82f89ce2d698ee71eb00cf15dc
Add PM_QUERY_DATA API to pass query data
EEMI call from Linux to PLM .
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I18735b72ab9cb62fb6cbc7582e77de6cb57f99b0
PM_INIT_FINALIZE is not required for versal. To use Linux
Zynqmp PM driver for versal, handle PM_INIT_FINALIZE API
in ATF for versal by always returning SUCCESS.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I6fe5445d78e713d70282ac8931ff8b17c96b2a14
PM_GET_TRUSTZONE_VERSION API is required to use zynqmp-firmware
driver for versal. Add support of PM_GET_TRUSTZONE_VERSION API
for versal.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ie1c859890096024cc8be67386e3fd0f5f8a4385f
As IPI mailbox service is common to both ZynqMP and Versal,
move it to xilinx/common.
Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I1a7008ccf7930829621147922d2c6d8d46df5502
Add PM IOCTL EEMI.
Below PLL related IOCTLs are not available in versal PLM.
* IOCTL_SET_PLL_FRAC_MODE
* IOCTL_GET_PLL_FRAC_MODE
* IOCTL_SET_PLL_FRAC_DATA
* IOCTL_SET_PLL_FRAC_DATA
PLM has new EEMI APIs for PLL related operations.
Call them instead of passing IOCTL API to PLM.
For other IOCTL, ATF just pass through IOCTL
request to PLM (Platform Loader and Manager).
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I96f8da46a4d3965c9291b7b2da96056408137839
Add power down/restart related below API
- Force power down
- System shutdown
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Icd4a922923b1fd50eca1f5361f1e604aedcdb529
Add SMC handler for EEMI API calls coming from EL1/EL2.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: If0ef2a1f2cfc2747be6b91828371bcbec56b1e15
Implement below pin control related APIs:
- Request pin
- Release pin
- Set pin function
- Get pin function
- Set pin parameter value
- Get pin parameter value
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ib805cc8c936b63206d44bf1f7bebd0f03f7b3c01
Add support for EEMI API get_api_verion.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic1ef90a194ae6164994a7fc5d8ff0b7b192636fe
Port ZynqMP PM services for versal to send PM APIs to PMC
using IPI.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I27a52faf27f1a2919213498276a6885a177cb6da
Move versal_def.h to platform specific include directory.
Also, update source file to include header file from updated
path of versal_def.h
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I313592a17552843b9cc7048f31bcaaefa40ffd91
Move versal_private.h to platform specific include directory.
Also, rename it to plat_private.h instead of having platform
name. So, it can be used to common source files which needs
platform specific data.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I65eefbea7722ffa2760b992491c00eebef5bcef4
- Flag GICV2_G0_FOR_EL3 needs to be set for group interrupts
to be targeted to EL3.
- Raise SGI interrupts for individual CPU cores as GIC API
uses CPU num as parameter, not CPU mask.
- Flag WARMBOOT_ENABLE_DCACHE_EARLY needs to be set to enable
CPU interface mask work properly for all CPU cores which is
required when generating SGI.
- Call plat_ic_end_of_interrupt() from ttc_fiq_handler() to clear
GIC interrupt to avoid same interrupt again.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I71d4935b8d4688a3729c62753ca8a1a77cd92ae7
This patch adds support for CRC checksum for IPI data when the
macro ZYNQMP_IPI_CRC_CHECK is defined.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic981f162666b3c1fffeb1b9fef3ee7714ecd889d
UEFI decompression will fail if the payload size is too large and the load
address is too low. This patch moves the payload to a higher address to fix
the issue
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I36087fbd2237b62891c59dbe2d34336bddfaa396
All function in socfpga_sip_svc.c should only be called locally except
sip_smc_handler().
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib84ef9a2e521967baa4cfd32e6bc569dd3a5d2f5
Now that there is plenty of space (32 KiB) available for NOBITS
sections, we can afford using an entire page for coherent memory. In
fact, because it simplifies the code, this is a beneficial change for
loaded image (.text) size, where we are still close to the size limit.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I0b899dabcb162015c63b0e4aed0869569c889ed9
Implements a way to add platform specific power off code to a
Marvell Armada 8K platform.
Marvell Armada 8K boards can now add a board/system_power.c file
that contains a system_power_off() function.
This function can now send a command to a power management MCU or
other board periferals before shutting the board down.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: Iaba20bc2f603195679c54ad12c0c18962dd8e3db
---
I am working on a device that will be ported later, which has a
custom power management MCU that handles LEDs, board power and fans
and requires this separation.
Add missing #address-cells and #size-cells into generated DT, otherwise
the DT is invalid. While the parsers thus far handled this correctly via
various fallbacks, this is not applicable in the long run, so fix this.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ic808a3b27b93e5258ec1a19acc3d593e53625c15
Add new QID to get maximum supported divisor by clock.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I35fc92457e522f3f0614d983c21e55c2b0b8e80a
Existing implementation does not allow to change the value of the
DIV1 because DIV2 does not have SET_RATE_PARENT flag.
This causes DIV1 value to be fixed and only value of DIV2 will be
adjusted according to required clock rate.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b
Linux expects custom flags in type flags. So move
custom flags to type flags instead of providing
them to clock core flags.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I668a8084d966815a9d9e86c2b18ecb5b18cb6b78
Add support to add extra custom type flags and provide
to caller in topology query.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Id9cc065dbadfed2291dd4f62674d7838da4cdf40
Add GET_CALLBACK_DATA function again as now Linux driver
supports both mailbox as well as ISR method.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ieb99d61976e1cb718fcd1021d9cf4958e7556c81
* changes:
zynqmp: pm: Add LPD WDT clock to the pm_clock structure
zynqmp: pm: Fix clock models and IDs of GEM-related clocks
zynqmp: pm: Rename FPD WDT clock ID
plat: xilinx: zynqmp: Correct syscnt freq for QEMU
arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR
arm64: zynqmp: Add id for new RFSoC device ZU39DR
This patch removes un-needed r/w parameter checks for qspi driver. The
driver can actually access any offset and size.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: If60b2c016aa91e2c24ddc57c6ad410c8dc5dcf53
This patch fixes the violations of Rule 21.1 from all the
header files.
Rule 21.1 "#define and #undef shall not be used on a reserved
identifier or reserved macro name"
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I12e17a5d7158defd33b03416daab3049749905fc
This patch fixes the violations of Rule 21.1 from all the
Tegra common header files.
Rule 21.1 "#define and #undef shall not be used on a reserved
identifier or reserved macro name"
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I2e117645c110e04c13fa86ebbbb38df4951d2185
NOTE for platform integrators:
API `plat_psci_stat_get_residency()` third argument
`last_cpu_idx` is changed from "signed int" to the
"unsigned int" type.
Issue / Trouble points
1. cpu_idx is used as mix of `unsigned int` and `signed int` in code
with typecasting at some places leading to coverity issues.
2. Underlying platform API's return cpu_idx as `unsigned int`
and comparison is performed with platform specific defines
`PLAFORM_xxx` which is not consistent
Misra Rule 10.4:
The value of a complex expression of integer type may only be cast to
a type that is narrower and of the same signedness as the underlying
type of the expression.
Based on above points, cpu_idx is kept as `unsigned int` to match
the API's and low-level functions and platform defines are updated
where ever required
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c
This patch removes re-definition of the following FVP build
options from plat\arm\board\fvp\fvp_def.h:
'FVP_CLUSTER_COUNT'
'FVP_MAX_CPUS_PER_CLUSTER'
'FVP_MAX_PE_PER_CPU'
which are set in platform.mk.
This fixes a potential problem when a build option set in
platform.mk file can be re-defined in fvp_def.h header file
used by other build component with a different makefile which
does not set this option.
Ref. GENFW-3505.
Change-Id: I4288629920516acf2c239c7b733f92a0c5a812ff
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
In further patches, we aim to enable -Wredundant-decls by default.
This rearragement of helper macros is necessary to make Coverity
tool happy as well as making sure there are no redundant function
declarations for PMF related declarations.
Also, PMF related macros were added to provide appropriate function
declarations for helper APIs which capture PSCI statistics.
Change-Id: I36273032dde8fa079ef71235ed3a4629c5bfd981
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.
Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
The MCE driver's helper functions were using postive values as error
codes.
This patch updates the functions to return negative values as error
codes instead. Some functions are updated to use the right error code.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3e2ecc30a6272a357e1a22ec850543fde2a694f6
CLK_TOPSW_LSBUS is parent of WDT clock. Clock from invalid
clock list would not be registered to CCF framework and so
cannot be used as parent of other clocks.
WDT clock has default parent as CLK_TOPSW_LSBUS(APB clock).
If CLK_TOPSW_LSBUS is not registered, CCF would not recognize
that clock and hence rate of WDT clock would be calculated to
be 0 by CCF(as parent rate is considered 0).
So it is necessary to allow registration of CLK_TOPSW_LSBUS
clock.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Iceaba0f137784fc5fd666e66ffc4c143381c6ccc
This patch adds LPD WDT clock node to the pm_clock clocks structure list
so that LPD WDT can be used from Linux.
Also this patch removes the CLK_LPD_LSBUS from invalid clock list to
allow the registration of this clock to CCF framework as it is the
parent of LPD WDT.
Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Iea065aa8150eaba4bb4b42bc6be1fd4b7fe7b403
GEM-related clock models were incorrect and are fixed as follows
(documented below for GEM0, but the same holds for any GEM ID):
- CLK_GEM0_REF_UNGATED represents clock that has DIV0/1 divisors and
the multiplexer controllable in GEM0_REF_CTRL (CRL_APB). The ID of this
clock is newly introduced in this patch.
- CLK_GEM0_REF models the clock mux that selects the reference clock
for Tx, i.e. selects CLK_GEM0_REF_UNGATED or external Tx clock. This
mux is controllable via GEM_CLK_CTRL (IOU_SLCR), bit GEM0_REF_SRC_SEL.
Note that the routing of external clock to the mux is not modelled
and is assumed to be configured by the FSBL if required, and not
changeable at runtime. The ID of this clock is introduced in this patch.
- CLK_GEM0_TX models clock with only a gate that is controlled via
bit 25 in GEM0_REF_CTRL (CRL_APB). The parent of this clock is
CLK_GEM0_REF. The clock ID of CLK_GEM0_TX matches the previous ID
value of CLK_GEM0_REF. This is done in order to fix the clock models
and incorrect binding without requiring to change device-tree (binding
of clock IDs to GEM interface).
- CLK_GEM0_RX models clock that has only gate controlled via RX_CLKACT
bit (26) in GEM0_REF_CTRL (CRL_APB). Parent of this clock is sourced
from external RGMII PHY (via MIO or EMIO). We do not model the whole
clock path to the Rx gate, since this is configured by the FSBL and
never changed at runtime (and there is no mechanism to change the
path at runtime). The clock ID of CLK_GEM0_RX clock is equal to the
previous ID value of CLK_GEM0_TX clock. This is done because the TX/RX
were swapped in device tree, so by fixing the IDs this way there is no
need for device tree fix.
Rates of the external RX/TX clocks can be specified in device tree if
needed. Right now, that's not necessary because Tx clock is sourced
from an on-chip PLL (via CLK_GEM0_REF_UNGATED/CLK_GEM0_REF), whereas
the Rx clock is sourced from external reference and the driver never
attempts to get/get clock rate (only to enable it). If this changes in
future, ATF clock model doesn't need to be changed. Instead, the clock
rates for gem0_tx_ext and gem0_rx_ext have to be specified in device
tree.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <will.wong@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I6497d4309e92205c527bd81b3aa932f4474f5b79
This patch renames FPD WDT clock ID from CLK_WDT to CLK_FPD_WDT.
Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I4d00a59b1dc54920115a2da55e8a06347fe2231c
Correct the syscnt frequency for ZynqMP QEMU to 65Mhz.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ie0137feb9b7e24ed4e5d6cbf81c58ac77bb69214
Add support for zu48dr and zu49dr to the list of zynqmp devices. The
zu48dr and zu49dr are the new RFSoC silicons with id values of 0x7b
and 0x7e.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I2978f16bb663853951ef8059bf0327f909447f34
This patch adds new RFSoC device ZU39DR to zynqmp
devices list
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I35735da9e7d7facbde44323c49eac1b714e4909d
The reclaim init code functionality relies on forward reference in the
linker script. The LLVM linker does not process it correctly.
Change-Id: I993aeb9587bfa07af25b60ed823a6a2c5e970c94
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Point boot address to DDR location for booting A5DS FPGA
FIP, Kernel and rootfs are sideloaded to DDR
Also move BL2 to higher address in DDR
Change-Id: Ia2a57a0bda776a1a0a96bcd3cfb5c6cd2cf4dc04
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
Correct the system, timer and uart frequencies to successfully run
the stack on FPGA
Correct Cortex-A5MPcore to 8 word granularity for Cache writeback
Change-Id: I2c59c26b7dca440791ad39f2297c68ae513da7b6
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
Pass DT to OpTee OS, so that OpTee OS can extract NSEC RAM layout from the DT.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I7d5ebae8d7ab9c70f079e30563d66bbd6a8ac7a4
Now that DDR drivers are mostly cleaned up , move them out of staging.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9de63f847a0ef9ac27a79fb0f848c351fd7f4da6
The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.
The SCU functions are to:
- maintain data cache coherency between the Cortex-A5/Cortex-A9
processors
- initiate L2 AXI memory accesses
- arbitrate between Cortex-A5/Cortex-A9 processors requesting
L2 accesses
- manage ACP accesses.
Snoop Control Unit will enable to snoop on other CPUs caches.
This is very important when it comes to synchronizing data between
CPUs. As an example, there is a high chance that data might be
cache'd and other CPUs can't see the change. In such cases,
if snoop control unit is enabled, data is synchoronized immediately
between CPUs and the changes are visible to other CPUs.
This driver provides functionality to enable SCU as well as enabling
user to know the following
- number of CPUs present
- is a particular CPU operating in SMP mode or AMP mode
- data cache size of a particular CPU
- does SCU has ACP port
- is L2CPRESENT
Change-Id: I0d977970154fa60df57caf449200d471f02312a0
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
So far we have seen two different clock setups for the Raspberry Pi 4
board, with the VPU clock divider being different. This was handled by
reading the divider register and adjusting the base clock rate
accordingly.
Recently a new GPU firmware version appeared that changed the clock rate
*again*, though this time at a higher level, so the VPU rate (and the
apparent PLLC parent clock) did not seem to change, judging by reading
the clock registers.
So rather than playing cat and mouse with the GPU firmware or going
further down the rabbit hole of exploring the whole clock tree, let's
just skip the baud rate programming altogether. This works because the
GPU firmware actually sets up and programs the debug UART already, so
we can just use it.
Pass 0 as the base clock rate to let the console driver skip the setup,
also remove the no longer needed clock code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ica88a3f3c9c11059357c1e6dd8f7a4d9b1f98fd7
Increase calibration delay to cater for HPS 1st mode and
reduce clear emif delay which takes too long
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1a50a5d8a6518ba085d853cb636efa07326552b4
Add support for platform specific warm-reset through psci system reset 2.
- system_reset2 implementation that calls for l2 cache reset
- Check for magic number and request for warm reset in bl2
- Create a shared reset manager header file for Agilex and Stratix 10
- Clean up parameter info in plat_get_next_bl_params
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3fdd9a2711c80d9bd3dc05b81527781d840bd726
Enable access to secure registers by non-secure world through secure
monitor calls
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I80610e08c7cf31f17f47a7597c269131a8de2491
This frees up space in SRAM A2 that will be used by the SCP firmware and
SCPI shared memory.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I8ce035257451e2d142666fe0cd045e59d4d57b35
All the SoCs in 64-bit UniPhier SoC family support EL2.
Just hard-code MODE_EL2 instead of using el_implemented() helper.
Change-Id: I7ab48002c5205bc8c013e1b46313b57d6c431db0
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
spm resume will restore Vmodem/Vcore voltages
back based on the SPM_DVS_LEVEL.
Change-Id: I37ff7ce4ba62219c1858acea816c5bc9ce6c493e
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
uniphier_scp_is_running() reads the UNIPHIER_STMBE2COM register,
but it does not exist on all SoCs.
Do not call this function if the on-chip SCP is not supported.
Change-Id: I7c71ca0735e3a8e095c3f22ba6165f82a2986362
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The contents of this header have been merged into the spm_mm_svc.h
header file.
Change-Id: I01530b2e4ec1b4c091ce339758025e2216e740a4
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Before adding any new SPM-related components we should first do
some cleanup around the existing SPM-MM implementation. The aim
is to make sure that any SPM-MM components have names that clearly
indicate that they are MM-related. Otherwise, when adding new SPM
code, it could quickly become confusing as it would be unclear to
which component the code belongs.
The secure_partition.h header is a clear example of this, as the
name is generic so it could easily apply to any SPM-related code,
when it is in fact SPM-MM specific.
This patch renames the file and the two structures defined within
it, and then modifies any references in files that use the header.
Change-Id: I44bd95fab774c358178b3e81262a16da500fda26
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
The Secure Partition Manager (SPM) prototype implementation is
being removed. This is preparatory work for putting in place a
dispatcher component that, in turn, enables partition managers
at S-EL2 / S-EL1.
This patch removes:
- The core service files (std_svc/spm)
- The Resource Descriptor headers (include/services)
- SPRT protocol support and service definitions
- SPCI protocol support and service definitions
Change-Id: Iaade6f6422eaf9a71187b1e2a4dffd7fb8766426
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
There are two different implementations of Secure Partition
management in TF-A. One is based on the "Management Mode" (MM)
design, the other is based on the Secure Partition Client Interface
(SPCI) specification. Currently there is a dependency between their
build flags that shouldn't exist, making further development
harder than it should be. This patch removes that
dependency, making the two flags function independently.
Before: ENABLE_SPM=1 is required for using either implementation.
By default, the SPCI-based implementation is enabled and
this is overridden if SPM_MM=1.
After: ENABLE_SPM=1 enables the SPCI-based implementation.
SPM_MM=1 enables the MM-based implementation.
The two build flags are mutually exclusive.
Note that the name of the ENABLE_SPM flag remains a bit
ambiguous - this will be improved in a subsequent patch. For this
patch the intention was to leave the name as-is so that it is
easier to track the changes that were made.
Change-Id: I8e64ee545d811c7000f27e8dc8ebb977d670608a
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
This patch fixes the bug in BL2 dynamic configuration initialisation
which prevents loading NT_FW_CONFIG image (ref. GENFW-3471).
It also adds parentheses around 'if' statement conditions to fix
Coverity defect.
Change-Id: I353566c29b84341887e13bf8098a4fedfc4e00ff
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This patch saves the boot parameters provided by the previous bootloader
during cold boot and passes them to Trusty. Commit 06ff251ec introduced
the plat_trusty_set_boot_args() handler, but did not consider the boot
parameters passed by the previous bootloader. This patch fixes that
anomaly.
Change-Id: Ib40dcd02b67c94cea5cefce09edb0be4a998db37
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Provide an SMC interface to the 9p filesystem. This permits
accessing firmware drivers through a common interface, using
standardized read/write/control operations.
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I9314662314bb060f6bc02714476574da158b2a7d
This patch enables per-CPU GIC CPU interfaces during CPU
power on. The previous code initialized the distributor
for all CPUs, which was not required.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifd957b2367da06405b4c3e2225411adbaec35bb8
Ported the pmf asm macros and the asm code in the bl31 entrypoint
necessary for the instrumentation to AArch32.
Since smc dispatch is handled by the bl32 payload on AArch32, we
provide this service only if AARCH32_SP=sp_min is set.
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: Id33b7e9762ae86a4f4b40d7f1b37a90e5130c8ac
Switching execution states is only possible if EL3 is AArch64.
As such there is no need to validate the entrypoint on AArch32 builds.
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: I3c1eb25b5df296a492870641d274bf65213c6608
Enable the workaround for Cortex-A53 erratum 855873 for the Rockchip
RK3328, silencing a warning at startup.
Change-Id: I5aa29d674d23c096c599abcb5e7dac970f9607d8
Signed-off-by: Simon South <simon@simonsouth.net>
Fixes the SiP Service driver that is responsible for FPGA
reconfiguration. Also change the base address of FPGA reconfiguration
to 0x400000.
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I2b84c12c85cd5fc235247131fec4916ed2fb56c8
There are a few issues in mailbox that needs to be fixed.
- Send doorbell after an indirect cmd
- Do not ring doorbell when polling mailbox response as it should've been
sent by send_cmd
- remove unneeded cmd_free_offset check
- Fix mailbox initialization
- Fix get_config_status returning a wrong status when the status is busy
- Add command length in mailbox command header
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: If613e2ca889a540a616c62d69ad0086a7cd46536
* changes:
rockchip: make miniloader ddr_parameter handling optional
rockchip: px30: cleanup securing of ddr regions
rockchip: px30: move secure init to separate file
rockchip: really use base+size for secure ddr regions
rockchip: bring TZRAM_SIZE values in line
Transfering the regions of ddr memory to additionally protect is very much
specific to some rockchip internal first stage bootloader and doesn't get
used in either mainline uboot or even Rockchip's published vendor uboot
sources.
This results in a big error
ERROR: over or zero region, nr=0, max=10
getting emitted on every boot for most users and such a message coming
from early firmware might actually confuse developers working with the
system.
As this mechanism seems to be only be used by Rockchip's internal miniloader
hide it behind a build conditional, so it doesn't confuse people too much.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I52c02decc60fd431ea78c7486cad5bac82bdbfbe
So far the px30-related ddr security was loading data for regions to secure
from a pre-specified memory location and also setting region0 to secure
the first megabyte of memory in hard-coded setting (top=0, end=0, meaning
1MB).
To make things more explicit and easier to read add a function doing
the settings for specified memory areas, like other socs have and also
add an assert to make sure any descriptor read from memory does not
overlap the TZRAM security in region0 and TEE security in region1.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I78441875112bf66a62fde5f1789f4e52a78ef95f
Similar to others like rk3399 and rk3288 move the secure init to a
separate file to unclutter the soc init a bit.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: Iebb38e24f1c7fe5353f139c896fb8ca769bf9691
Add-in support for handling BL31 parameter from non-BL2 image, ie. SPL
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I16118d791399f652b6d1093c10092935a3449c32
Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use
of On-Chip RAM for BL31 specific variables filling down from handoff
offset to reduce fragmentation
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib64f48bd14f71e5fca2d406f4ede3386f2881099
This patch will provide an entrypoint for uboot's spl into BL31.
BL31 will also handle secondary cpu state during uboot's cold boot
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I661bdb782c2d793d5fc3c7f78dd7ff746e33b7a3
Move the get_config_status out of sip_svc driver.
Modify the function so that it can return either
CONFIG_STATUS or RECONFIG_STATUS
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I642d5900339e67f98be61380edc2b838e0dd47af
Separate SiP related definition from mailbox header file
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I45ba540f29d9261007f7ec23469358747cf140b4
The calls to secure ddr regions on rk3288 and rk3399 use parameters of
base and size - as it custom for specifying memory regions, but the
functions themself expect start and endpoints of the area.
This only works by chance for the TZRAM, as it starts a 0x0 and therefore
its end location is the same as its size.
To not fall into a trap later on adapt the functions to really take
base+size parameters.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: Idb9fab38aa081f3335a4eca971e7b7f6757fbbab
The agreed upon division of early boot locations is 0x40000 for bl31
to leave enough room for u-boot-spl and 0x100000 for bl33 (u-boot).
rk3288 and rk3399 already correctly secure the ddr up to the 1MB boundary
so pull the other platforms along to also give the Rockchip TF-A enough
room to comfortably live in.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: Ie9e0c927d3074a418b6fd23b599d2ed7c15c8c6f
Chip ID checking and poweroff work just like they did before.
Regulators are now enabled just like on A64/H5.
This changes the signatures of the low-level register read/write
functions to match the interface expected by the common driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I14d63d171a094fa1375904928270fa3e21761646
Previously, the A64/H5 and H6 platforms' PMIC setup code was entirely
independent. However, some H6 boards also need early regulator setup.
Most of the register interface and all of the device tree traversal code
can be reused between the AXP803 and AXP805. The main difference is the
hardware bus interface, so that part is left to the platforms. The
remainder is moved into a driver.
I factored out the bits that were obviously specific to the AXP803;
additional changes for compatibility with other PMICs can be made as
needed.
The only functional change is that rsb_init() now checks the PMIC's chip
ID register against the expected value. This was already being done in
the H6 version of the code.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Icdcf9edd6565f78cccc503922405129ac27e08a2
This simplifies the code a bit. Verified to produce the same binary.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie1ec1ce2ea39c46525840906826c90a8a7eff287
As of a561e41bf1 ("allwinner: power: add enable switches for DCDC1/5")
there are no longer regulators without an enable register provided.
Since it seems reasonable that this will continue to be the case, drop
the check.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Icd7ec26fc6450d053e6e6d855fc16229b1d65a39
should_enable_regulator() is already checked in the regulators subnode
loop before setup_regulator() is called, so there's no need to check it
again here.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Idb8b8a6e435246f4fb226bc84813449d80a0a977
These are used by the PMIC setup code, which runs during BL31
initialization, and the PSCI shutdown code, also a part of BL31.
They can't be needed before BL31, or it wouldn't be possible to boot.
Allwinner platforms don't generally build anything but BL31 anyway, but
this change improves clarity and consistency with allwinner-common.mk.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I24f1d9ca8b4256e44badf5218d04d8690082babf
The function is only used in this file, and it doesn't make sense for it
to be used anywhere else.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iab18f082911edcdbc37ceeaff8c512be68e0cb0f
The action of last resort isn't going to change between SoCs. This moves
that code back to the PSCI implementation, where it more obviously
matches the code in sunxi_system_reset().
The two error messages say essentially the same thing anyway.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I62ac35fdb5ed78a016e9b18281416f1dcea38a4a
- Check the return value from sunxi_init_platform_r_twi().
- Print the PMIC banner before doing anything that might fail.
- Remove double prefixes in error messages.
- Consistently omit the trailing period.
- No need to print the unknown SoC's ID, since we already did that
earlier in bl31_platform_setup().
- On the other hand, do print the ID of the unknown PMIC.
- Try to keep the messages concise, as the large string size in these
files was causing the firmware to spill into the next page.
- Downgrade the banner from NOTICE to INFO. It's purely informational,
and people should be using debug builds on untested hardware anyway.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ib909408a5fdaebe05470fbce48d245dd0bf040eb
Ensure that the default (zero) value represents the case where we take
no action. Previously, if a PLAT=sun50i_a64 build was booted on an
unknown SoC ID, it would be treated as an H5 at shutdown.
This removes some duplicate code and fixes error propagation on H6.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I4e51d8a43a56eccb0d8088593cb9908e52e782bc
The clock must be running for the module to be reset.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ic8fafc946f3a1a697174b91288e357ffa033ab9a
Instead of stringizing the paths to binary files, add them as string
defines on the command line (e.g. -DFOO=\"BAR\" instead of -DFOO=BAR).
This prevents macros from being expanded inside the string value itself.
For example, -DFOO=/path/with-linux-in-it would have been expanded to
"/path/with-1-in-it" because `linux=1` is one of the standard GCC
defines.
Change-Id: I7b65df3c9930faed4f1aff75ad726982ae3671e6
Signed-off-by: Joshua Watt <JPEWhacker@gmail.com>
HDCP is using a binary driver, add macro PLAT_RK_DP_HDCP to make it as
an option.
Change-Id: I54ef1a3635a28e8ae56654bd1e91dfe011520a7f
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory
as both has been refactored to common directory for sharing with agilex
platform
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I395fed66408f536e8fefd637681e742c63621818
C99 standard: "What constitutes an access to an object that has
volatile-qualified type is implementation-defined".
GCC is not considering the cast to void of volatile structures as an
access and so is not actually issuing reads.
Clang does read those structures by copying them on the stack, which in
this case creates an overflow because of their large size.
This patch removes the cast to void and instead uses the USED attribute
to tell the compiler to retain the static variables.
Change-Id: I952b5056e3f6e91841e7ef9558434352710ab80d
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Zelalem Aweke <zelalem.aweke@arm.com>
This patch fixes hangs that happen after soft resetting of rk3399.
Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
Change-Id: If41b12ba1dfcb2ba937361b58eafd50bf5c483d4
Tegra194 supports multiple SMMU blocks. This patch adds support to
save register values for SMMU0 and SMMU2, before entering the System
Suspend state.
Change-Id: I3a376cdb606ea057ad7047714717245f9dced5cf
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
This patch updates the memory address space, physical and virtual,
to be 40-bits wide for all Tegra194 platforms.
Change-Id: Ie1bcdec2c4e8e15975048ce1c2a31c2ae0dd494c
Signed-off-by: Steven Kao <skao@nvidia.com>
The per CPU wake times are saved in an array called 't19x_percpu_data'. But,
there is one instance in the code where the name of the variable is misspelt.
This patch fixes this typographical error to fix compilation errors.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I52f5f0b150c51d8cc38372675415dec7944a7735
Previously the .init section was created even when the reclaim flag was
manually set to 0.
Change-Id: Ia9e7c7997261f54a4eca725d7ea605192f60bcf8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Zelalem Aweke <zelalem.aweke@arm.com>
Currently tb_fw_cfg_dtb size is fixed to max, which is generally a page
(but depend on the platform). Instead, read the actual size of the dtb
with the libfdt "fdt_totalsize" function.
This avoid flushing extra memory after updating the dtb with mbedtls
heap information when shared heap is used.
Change-Id: Ibec727661116429f486464a0c9f15e9760d7afe2
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
The hooks were populated but the power down left the CPU in limbo-land.
What we need to do - until there is a way to actually power off - is to
turn off the MMU and enter the spinning loop as if we were cold-booted.
This allows the on-call to pick up the CPU again.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: Iefc7a58424e3578ad3dd355a7bd6eaba4b412699
This is not conforming C and does not compile with -fno-common.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I6535954cc567d6efa06919069b91e3f50975b073
This was found by compiling with -fno-common:
./build/picopi/release/bl2/imx_snvs.o:(.bss.__packed+0x0): multiple definition of `__packed';
./build/picopi/release/bl2/imx_caam.o:(.bss.__packed+0x0): first defined here
__packed was intended to be the attribute macro from cdefs.h, not an
object of the structure type.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id02fac3f098be2d71c35c6b4a18012515532f32a
The current range check for the offset is wrong: it is counting bytes,
while indexing an array of uint32_t. Since the offset is always zero,
the parameter is unnecessary. Instead of adding more code to fix the
check, remove the parameter to avoid the problem entirely.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iadfc7d027155adc754e017b3462233ce9a1d64f6
* changes:
Tegra194: add support to reset GPU
Tegra194: memctrl: fix logic to check TZDRAM config register access
Tegra: introduce plat_enable_console()
Tegra: include: drivers: introduce spe.h
Tegra194: update nvg header to v6.4
Tegra194: mce: enable strict checking
Tegra194: CC6 state from last offline CPU in the cluster
Tegra194: console driver compilation from platform makefiles
Tegra194: memctrl: platform handler for TZDRAM setup
Tegra194: memctrl: override SE client as coherent
Tegra194: save system suspend entry marker to TZDRAM
Tegra194: helper functions for CPU rst handler and SMMU ctx offset
Tegra194: cleanup references to Tegra186
Tegra194: mce: display NVG header version during boot
Tegra194: mce: fix cg_cstate encoding format
Tegra194: drivers: SE and RNG1/PKA1 context save support
Tegra194: rename secure scratch register macros
Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation
Tegra194: mce: remove unsupported functionality
Tegra194: sanity check target cluster during core power on
Tegra194: fix defects flagged by MISRA scan
Tegra194: mce: fix defects flagged by MISRA scan
Tegra194: remove the GPU reset register macro
Tegra194: MC registers to allow CPU accesses to TZRAM
Tegra194: increase MAX_MMAP_REGIONS macro value
Tegra194: update nvg header to v6.1
Tegra194: update cache operations supported by the ROC
Tegra194: memctrl: platform handlers to reprogram MSS
Tegra194: core and cluster count values
Tegra194: correct the TEGRA_CAR_RESET_BASE macro value
Tegra194: add MC_SECURITY mask defines
Tegra194: Update wake mask, wake time for cpu offlining
Tegra194: program stream ids for XUSB
Tegra194: Update checks for c-state stats
Tegra194: smmu: fix mask for board revision id
Tegra194: smmu: ISO support
Tegra194: Initialize smmu on system suspend exit
Tegra194: Update cpu core-id calculation
Tegra194: read-modify-write ACTLR_ELx registers
Tegra194: Enable fake system suspend
Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bits
Tegra194: platform support for memctrl/smmu drivers
Tegra194: Support for cpu suspend
This patch adds macros, to define registers required to support GPU
reset, for Tegra194 SoCs.
Change-Id: Ifa7e0161b9e8de695a33856193f500b847a03526
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
This patch fixes the logic to check if the previous bootloader has
disabled access to the TZDRAM configuration registers. The polarity
for the bit was incorrect in the previous check.
Change-Id: I7a0ba4f7b1714997508ece904c0261ca2c901a03
Signed-off-by: Steven Kao <skao@nvidia.com>
This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while all the previous platforms support only one
console.
For Tegra194 platforms, the previous bootloader checks the platform
config and sets the uart-id boot parameter, to 0xFE. On seeing this
boot parameter, the platform port uses the proper memory aperture
base address to communicate with the SPE. This functionality is
currently protected by a platform macro, ENABLE_CONSOLE_SPE.
Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch introduces a header file for the spe-console driver. This
file currently provides a device struct and a registration function
call for clients.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ic65c056f5bd60871d8a3f44f2c1210035f878799
This patch updates the header, t194_nvg.h, to v6.4. This
gets it in synch with MTS pre-release 2 - cl39748439.
Change-Id: I1093c9f5dea7b7f230b3267c90b54b7f3005ecd7
Signed-off-by: Steven Kao <skao@nvidia.com>
Aditya Angadi
Vijayenthiran Subramaniam
Louis Mayencourt
Jerome Forissier
Sandrine Bailleux
Abdul Halim, Muhammad Hadi Asyrafi
Mark Dykes
Max Shvetsov
Carlo Caione
Zelalem
Varun Wadekar
Manish Pandey
Alexei Fedorov
Pritesh Raithatha
Grzegorz Jaszczyk
Tejas Patel
Andrew Walbran
Soby Mathew
Madhukar Pappireddy
Andrew F. Davis
Chris Kay
Deepika Bhavnani
Masahiro Yamada
Steven Kao
Puneet Saxena
Arto Merilainen
Vignesh Radhakrishnan
Venkatesh Yadav Abbarapu
Anthony Steinhauser
Norbert Werner
Samuel Holland
Lionel Debieve
Nicolas Le Bayon
Krishna Reddy
Siva Durga Prasad Paladugu
Saeed Nowshadi
Ravi Patel
Jolly Shah
Rajan Vaja
Wendy Liang
Tien Hock, Loh
Luka Kovacic
Marek Vasut
Olivier Deprez
Mounika Grace Akula
Mirela Simonovic
Edgar E. Iglesias
Ambroise Vincent
Avinash Mehta
Vishnu Banavath
Andre Przywara
Roger Lu
Paul Beesley
György Szing
Bence Szépkúti
Simon South
Heiko Stuebner
Joshua Watt
Ziyuan Xu
Piotr Szczepanik
Jan Kiszka
Jeetesh Burman